Sharp CDC2900 Service Manual - Page 48

IC1 VHiLA9241M/-1:Servo Amp.LA9241M 2/2

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CD-C622/C2900 IC1 VHiLA9241M/-1:Servo Amp.(LA9241M) (2/2) Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Port Name CL DAT CE DRF FSS VCC2 REFI VR LF2 PH1 BH1 LDD LDS VCC1 Function Micro computer command clock input pin. Micro computer command data input pin. Micro computer command chip enable input pin. (DETECT RF) RF level detection output. (Focus Serch Select) Pin to switch focus search mode. (± search/+ search for reference voltage) VCC pin for servo system and digital system. Pin to connect pass control for reference voltage. Reference voltage output pin. Pin to set defect detection time constant of disk. Pin to connect capacitor for peak hold of RF signal. Pin to connect capacitor for bottom hold of RF signal. APC circuit output pin. APC circuit output pin. RF system VCC pin. VCC1 64 FIN2 1 LDS LDD BH1 PH1 LP2 63 62 61 60 59 APC RF DET VR REFI VCC2 FSS DRF CE DAT CL CLK DEF 58 57 56 55 54 53 52 51 50 49 REF 48 NC FIN1 2 E3 F4 TB 5 TE- 6 TE 7 TESI 8 SCI 9 TH 10 TA 11 TD- 12 TD 13 JP 14 I/V VCA BAL VCA TE T.SERVO & T.LOGIC F.SERVO & F.LOGIC µ-COM SLC INTER FACE RF AMP SPINDLE SERVO SLED SERVO 47 TBC 46 FSC 45 DGND 44 SLI 43 SLC 42 RFS- 41 RFSM 40 CV+ 39 CV38 SLOF 37 HFL 36 TES 35 TOFF 34 TGL 33 JP+ TO 15 FD 16 17 18 19 FD- FA FA- 20 21 22 23 24 FE FE- AGND SNPC SPI 25 26 SPG SP- 27 28 SPD SLEQ 29 30 31 32 SLD SL- SL+ JP- Figure 48 BLOCK DIAGRAM OF IC - 48 -

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CD-C622/C2900
– 48 –
IC1 VHiLA9241M/-1:Servo Amp.(LA9241M) (2/2)
Pin No.
Port Name
Function
51
CL
Micro computer command clock input pin.
52
DAT
Micro computer command data input pin.
53
CE
Micro computer command chip enable input pin.
54
DRF
(DETECT RF) RF level detection output.
55
FSS
(Focus Serch Select)
Pin to switch focus search mode. (
±
search/+ search for reference voltage)
56
VCC2
VCC pin for servo system and digital system.
57
REFI
Pin to connect pass control for reference voltage.
58
VR
Reference voltage output pin.
59
LF2
Pin to set defect detection time constant of disk.
60
PH1
Pin to connect capacitor for peak hold of RF signal.
61
BH1
Pin to connect capacitor for bottom hold of RF signal.
62
LDD
APC circuit output pin.
63
LDS
APC circuit output pin.
64
VCC1
RF system VCC pin.
Figure 48 BLOCK DIAGRAM OF IC
1
FIN2
FIN1
E
F
TB
TE-
TE
TESI
SCI
TH
TA
TD-
TD
JP
TO
FD
FD-
FA
FA-
FE
FE- AGND SP
SPI
SPG
SP-
SPD
SLEQ
SLD
SL-
SL+
JP-
JP+
TGL
TOFF
TES
HFL
SLOF
CV-
CV+
RFSM
RFS-
SLC
SLI
DGND
FSC
TBC
NC
DEF
CLK
CL
DAT
CE
DRF
FSS
VCC2
REFI
VR
LP2
PH1
BH1
LDD
LDS
SLC
RF AMP
TE
F.SERVO & F.LOGIC
SPINDLE SERVO
SLED SERVO
VCC1
2
3
4
6
7
5
8
9
10
11
12
13
14
15
16
17
18
19
20
21
23
22
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
46
47
48
49
50
51
52
53
54
55
56
57
58
59
61
60
62
63
64
45
24
APC
RF DET
REF
VCA
VCA
INTER FACE
BAL
μ
-COM
I/V
T.SERVO & T.LOGIC
NC