Toshiba XM-7002B Product Specification - Page 20

6.2.3.Timing of Host Interface (DMA Multi) Figure 11 shows the Host Interface DMA multi word Timings DMARQ DMACK-*1 DIOR/DIOW-*1 Read DD0-1 Write DD0-1 t0 tD tK tI tE tF tL tJ tZ tG tH *1: In all timing diagrams, the low line indicator negated, and the upper line indicators asserted. Multi word DMA Mode 2 timing parameters min (ns) max (ns) Min time (ns) t0 Cycle time 120 tC DMACK to DMREQ delay tD DIOR-/DIOW- 16-bit 70 tE DIOR- data access tF DIOR- data hold 5 tZ DMACK- to tristate tG DIOR/DIOW- data setup 20 tH DIOW- data hold 10 tI DMACK to DIOR-/DIOW- setup 0 tJ DIOR-/DIOW- to DMACK hold 5 tKr DIOR- negated pulse width 25 tKw DIOW- negated pulse width 25 tLr DIOR- to DMREQ delay tLw DIOR- to DMREQ delay Figure 11 Host Interface Timing (DMA Multi) Max time (ns) --- 50 25 35 35 16/27 XM-7002B Rev.1.0