ViewSonic VA550 Service Manual - Page 17

ViewSonic

Corporation

Service

Manual

VA550

THEORY

OF

CIRCUIT

OPERATION

This

Product

supports

timing

from

VGA

to

XGA,

so

the

pixel

rate

is

from

25

MHz

to

80

MHz.

In

order

to

make

the

phases

of

the

sampling

clock

and

video

easier

to

adjust

when

the

using

the

fine

tune

function,

the

phase

delay

effect

in

the

high

pixel

rate

is

smaller

than

that

in

the

low

pixel

rate.

The

MPU

will

choose

the

proper

phase

adjustment

circuit

through

the

pin

4

of

IC25,

fine

tune

select.

The

fine

tune

control

is

a

PWM

signal.

When

I

2

C

changes

the

control

register

the

MPU

also

changes

the

fine

tune

control

duty

cycle.

The

changed

duty

cycle

will

become

DC

level

through

R89

and

C104.

When

a

pixel

rate

less

than

50

MHz

is

detected,

the

fine

tune

select

will

be

set

to

low

level.

R52,

R59,

R80

and

C103

are

all

phase

adjustment

components.

This

product

supports

DDC

1/2B

by

using

24LC21.

The

24LC21

is

a

128x

8

bits

EEPROM.

This

chip

is

designed

to

be

used

in

applications

requiring

storage

and

serial

transmission

of

configuration

and

control

information.

Two

modes

of

operation

have

been

implemented,

the

Transmit

Only

mode

and

Bi-Directional

mode.

Upon

power

up,

this

device

will

be

in

the

Transmit

Only

mode,

sending

a

serial

bit

stream

of

the

entire

memory

array

contents,

clocked

by

the

VCLK

pin.

A

valid

high

to

low

transition

on

the

SCL

pin

will

cause

the

device

to

enter

the

Bi-

Directional

mode

with

byte

selectable

read/write

capability

of

the

memory

array.

CONFIDENTIAL

—

DO

NOT

COPY

Page

15

ViewSonic VA550 Service Manual - Page 17

Va550, Confidential

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