AMD ADA4200DAA5BV Builders Guide - Page 10
Integrated DDR DRAM Memory Controller, HyperTransport™ Technology - processor
UPC - 683728133160
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Builder's Guide for AMD Athlon™ 64 Processor-Based Desktops and Workstations 31684 Rev. 3.00 September 2004 1.2 Integrated DDR DRAM Memory Controller The 64-/128-bit wide integrated DDR DRAM memory controller: • changes the way the processor accesses main memory, resulting in increased bandwidth, reduced memory latencies, and increased processor performance. • allows available memory bandwidth to scale with the number of processors and − can support up to eight registered DDR DIMMs with an AMD Athlon 64 FX processor. − can support up to four unbuffered DDR DIMMs with an AMD Athlon 64 939-pin processor. • has available memory bandwidth of up to 6.4 Gbytes/s (with PC3200). 1.3 HyperTransport™ Technology The HyperTransport technology of the AMD64 architecture offers the following features. • A scalable bandwidth interconnection between I/O subsystems and other chipsets • Up to 8.0 Gbytes/s bandwidth providing sufficient bandwidth for supporting new interconnects including PCI-X®, DDR, InfiniBand, and 10G Ethernet • Low power consumption (1.2 W) to help reduce the system thermal budget 1.4 Other Features of the AMD Athlon™ 64 Processor Other features of the AMD Athlon 64 processor include: • 64-bit wide key data and address paths that incorporate a 48-bit virtual address space and a 40-bit physical address space. • ECC (error correcting code) protection for L1 cache data, L2 cache data and tags, and DRAM with hardware scrubbing of all ECC-protected arrays. • Support for all instructions necessary to be fully compatible with SSE2 technology. • Two additional pipeline stages (compared to AMD's 32-bit architecture) for increased performance and frequency scalability. • Higher IPC (instructions-per-clock) achieved through additional key features, such as larger TLBs (translation lookaside buffer), flush filters, and enhanced branch prediction algorithms. 10 AMD Athlon™ 64 Processor Key Architectural Features Chapter 1