Asus A8V-E SE A8V-E SE User's Manual for English Edition - Page 65

DRAM Configuration The items in this sub-menu show the DRAM-related information auto-detected by the BIOS. Advanced Phoenix-Award BIOS CMOS Setup Utility DRAM Configuration Current DRAM Frequency Timing Mode x Memclock index value (MHz) x CAS# latency (Tcl) x Min RAS# active time(Tras) x RAS# to CAS# delay (Trcd) x Row precharge Time (Trp) x 1T/2T Memory Timing H/W DRAM Over 4G Remapping MTRR mapping mode Master ECC Enabled ECC Memory Interlock 200 MHz [Auto] 200Mhz 2.5 8T 4T 4T 2T [Enabled] [Continous] [Enabled] [At least One] Select Menu Item Specific Help Place an artificial memory clock limit on the system. Memory is prevented from running faster than this frequency. F1:Help ESC: Exit ↑↓ : Select Item →←: Select Menu -/+: Change Value Enter: Select Sub-menu F5: Setup Defaults F10: Save and Exit Current DRAM Frequency Shows the Transfer mode. This item is not configurable. Timing Mode [Auto] Sets the timing mode. Configuration options: [Auto] [Manual] Memclock index value (Mhz) [200Mhz] Sets the memory clock index value. Configuration options: [100Mhz] [133Mhz] [166Mhz] [200Mhz] [216Mhz] [233Mhz] [250Mhz] CAS# latency (Tcl) [2.5] Controls the latency between the SDRAM read command and the time the data actually becomes available. Configuration options: [2.0] [2.5] [3.0] Min RAS# active time (Tras) [8T] Sets the minimum RAS# active time. Configuration options: [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] RAS# to CAS# delay (Trcd) [4T] Controls the latency between the DDR SDRAM active command and the read/write command. Configuration options: [2] [3] [4] [5] [6] [7] ASUS A8V-E SE 2-23