EVGA 122-CK-NF63-TR User Manual - Page 126

Installing and Configuring the EVGA nForce 680i SLI Motherboard Memory Timing This section of the Adjust Motherboard Settings allows you to adjust various memory timings and cycles. When you select an option, information explaining the selection is displayed in the area below the Memory Timing box. Clicking on View SPD... displays a memory information window. This is for information only and is not editable. ‰ Row Address Strobe Adjusts the minimum RAS active time. This is the amount of time between a row being activated by Precharge and deactivated. A row cannot be deactivated until tRAS has completed. The lower this value, the faster the performance. However, if it is set too low it can cause data corruption by deactivating the row to soon. Adjustable from 1 to 63. ‰ Write Recovery Time Memory timing that determines the delay between a write command and a Precharge command is set to the same bank of memory. Adjustable from 1 to 15. ‰ W to R Termination Turnaround The Write-to-Read time is the number of clock cycles between the last write data pair and the subsequent READ command to the same physical block. Adjustable from 1 to 15. ‰ RAS to CAS access The RAS-to-CAS access (tRCD) is the amount of time in cycles for issuing an active command and the read/write commands. Adjustable from 1 to 15. 75