Foxconn A85GM English Manual. - Page 34

► CPU-NB HT Incoming Link Width / CPU-NB HT Outcoming Link Width - cpu support list

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3 contains important information about the module's speed, size, addressing mode and various other parameters, so that the motherboard memory controller (chipset) can better access the memory device. Select [Auto] for SPD enable mode.Select [Limit], the DRAM speed will not exceed the specified value listed in the "Memory Speed Adjust" item. If SPD value is faster than "Memory Speed Adjust" value, it will run at the specified "Memory Speed Adjust" speed. Otherwise, SPD value is selected.Select [Manual], then DRAM speed is manually selected according to the set value of "Memory Speed Adjust". ► GFX Engine Clock Override This item allows you to enable/disable GFX Engine Clock Override support. ► PCI Express Clock This option is used to adjust the speed of PCI Express slot. It can't enhance the graphics card speed. ► CPU Multiplier Adjust This option is used to adjust the CPU Clock Ratio. Multiply CPU clock with this ratio, you can get the CPU speed. Increase this ratio may overclock your CPU. ► Spread Spectrum If you enabled this function, it can significantly reduce the EMI (Electromagnetic Interference) generated by the system, so to comply with FCC regulation. But if overclocking is activated, you had better disable it. ► CPU-NB HT Link Speed HT stands for HyperTransport bus. The CPUNB HT Speed option controls the physical speed of the CPU to Northbridge HT link using multipliers ranging 1x to 13x. The physical speed of the link is determined by multiplying the CPU FSB with the CPUNB HT Speed setting. ► CPU-NB HT Incoming Link Width / CPU-NB HT Outcoming Link Width The coherency refers to the caching of memory, and the HT links between processors are coherent HT links as the HT protocol includes messages for managing the cache protocol. Other (non processor-processor) HT links are Non-Coherent HT links, as they do not have memory cache. The HyperTransport link width and frequency are initialized between the adjacent coherent and/or noncoherent HyperTransport technology devices during the reset sequence. It is highly recommended to set to [Auto] for overall performance. 27

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3
27
contains important information about the module’s speed, size, addressing mode and various
other parameters, so that the motherboard memory controller (chipset) can better access the
memory device. Select [Auto] for SPD enable mode.Select [Limit], the DRAM speed will not
exceed the specified value listed in the “Memory Speed Adjust” item. If SPD value is faster
than “Memory Speed Adjust” value, it will run at the specified “Memory Speed Adjust” speed.
Otherwise, SPD value is selected.Select [Manual], then DRAM speed is manually selected
according to the set value of “Memory Speed Adjust”.
► GFX Engine Clock Override
This item allows you to enable/disable GFX Engine Clock Override support.
► PCI Express Clock
This option is used to adjust the speed of PCI Express slot. It can't enhance the graphics card
speed.
► CPU Multiplier Adjust
This option is used to adjust the CPU Clock Ratio. Multiply CPU clock with this ratio, you can
get the CPU speed. Increase this ratio may overclock your CPU.
► Spread Spectrum
If you enabled this function, it can significantly reduce the EMI (Electromagnetic Interference)
generated by the system, so to comply with FCC regulation. But if overclocking is activated,
you had better disable it.
► CPU-NB HT Link Speed
HT stands for HyperTransport bus. The CPU<->NB HT Speed option controls the physical
speed of the CPU to Northbridge HT link using multipliers ranging 1x to 13x. The physical
speed of the link is determined by multiplying the CPU FSB with the CPU<->NB HT Speed
setting.
► CPU-NB HT Incoming Link Width / CPU-NB HT Outcoming Link Width
The coherency refers to the caching of memory, and the HT links between processors are co-
herent HT links as the HT protocol includes messages for managing the cache protocol. Other
(non processor-processor) HT links are Non-Coherent HT links, as they do not have memory
cache.
The HyperTransport link width and frequency are initialized between the adjacent coherent
and/or noncoherent HyperTransport technology devices during the reset sequence.
It is highly recommended to set to [Auto] for overall performance.