Home » Fujitsu Manuals » Hard Drives » Fujitsu MJA2500BH » Manual Viewer

Fujitsu MJA2500BH Maintenance Manual - Page 67

Read circuit, 4.6.4 Digital PLL circuit

Add to My Manuals
Save this manual to your list of manuals

Page 67 highlights

4.6 Read/write Circuit 4.6.3 Read circuit The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the flash digitizer circuit. This signal is converted into the read data by the decoder circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit. (1) AGC circuit The AGC circuit automatically regulates the output amplitude to a constant value even when the input amplitude level fluctuates. The AGC amplifier output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer/inner head positions. (2) Programmable filter circuit The programmable filter circuit has a low-pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost-up function that equalizes the waveform of the read signal. Cut-off frequency of the low-pass filter and boost-up gain are controlled from the register in read channel block. The MPU optimizes the cut-off frequency and boost-up gain according to the transfer frequency of each zone. (3) FIR circuit This circuit is 10-tap sampled analog transversal filter circuit that equalizes the head read signal to the Modified Extended Partial Response (MEEPR) waveform. (4) A/D converter circuit This circuit changes Sampled Read Data Pulse from the FIR circuit into Digital Read Data. (5) Viterbi detection circuit The sample hold waveform output from the flash digitizer circuit is sent to the Viterbi detection circuit. The Viterbi detection circuit demodulates data according to the survivor path sequence. 4.6.4 Digital PLL circuit The drive uses constant density recording to increase total capacity. This is different from the conventional method of recording data with a fixed data transfer rate at all data area. In the constant density recording method, data area is divided into zones by radius and the data transfer rate is set so that the recording density of the inner cylinder of each zone is nearly constant. The drive divides data area into 30 zones to set the data transfer rate. The MPU set the data transfer rate setup data (SD/SC) to the RDC block that includes the Digital PLL circuit to change the data transfer rate. C141-E293 4-11

Section	Page
Front Cover	1
FOR SAFE OPERATION	2
Revision History	3
Preface	5
Important Alert Items	9
Manual Organization	11
Contents	13
Illustrations	19
Figures	19
Tables	21
CHAPTER 1 Device Overview	23
1.1 Features	24
1.1.1 Functions and performance	24
1.1.2 Adaptability	24
1.1.3 Interface	25
1.2 Device Specifications	27
1.2.1 Specifications summary	27
1.2.2 Model and product number	28
1.3 Power Requirements	29
1.4 Environmental Specifications	32
1.5 Acoustic Noise	33
1.6 Shock and Vibration	33
1.7 Reliability	34
1.8 Error Rate	35
1.9 Media Defects	35
1.10 Load/Unload Function	35
1.10.1 Recommended power-off sequence	36
1.11 Advanced Power Management (APM)	36
1.12 Interface Power Management (IPM)	38
1.12.1 Host-initiated interface power management (HIPM)	38
1.12.2 Device-initiated interface power management (DIPM)	38
CHAPTER 2 Device Configuration	41
2.1 Device Configuration	42
2.2 System Configuration	43
2.2.1 SATA interface	43
2.2.2 Drive connection	43
CHAPTER 3 Installation Conditions	45
3.1 Dimensions	46
3.2 Mounting	47
3.3 Connections with Host System	53
3.3.1 Device connector	53
3.3.2 Signal segment and power supply segment	54
3.3.3 Connector specifications for host system	54
3.3.4 SATA interface cable connection	55
3.3.5 Note about SATA interface cable connection	55
CHAPTER 4 Theory of Device Operation	57
4.1 Outline	58
4.2 Subassemblies	58
4.2.1 Disk	58
4.2.2 Spindle	58
4.2.3 Actuator	58
4.2.4 Air filter	59
4.3 Circuit Configuration	59
4.4 Power-on Sequence	62
4.5 Self-calibration	64
4.5.1 Self-calibration contents	64
4.5.2 Execution timing of self-calibration	65
4.5.3 Command processing during self-calibration	65
4.6 Read/write Circuit	66
4.6.1 Read/write preamplifier (PreAMP)	66
4.6.2 Write circuit	66
4.6.3 Read circuit	67
4.6.4 Digital PLL circuit	67
4.7 Servo Control	68
4.7.1 Servo control circuit	68
4.7.2 Data-surface servo format	70
4.7.3 Servo frame format	72
4.7.4 Actuator motor control	73
4.7.5 Spindle motor control	74
CHAPTER 5 Interface	75
5.1 Physical Interface	76
5.1.1 Interface signals	76
5.1.2 Signal interface regulation	78
5.1.3 Electrical specifications	80
5.1.4 Connector pinouts	81
5.1.5 P11 function	82
5.1.6 Hot Plug	84
5.2 Logical Interface	85
5.2.1 Communication layers	86
5.2.2 Outline of the Shadow Block Register	87
5.2.3 Outline of the frame information structure (FIS)	88
5.2.4 Shadow block registers	96
5.3 Host Commands	101
5.3.1 Command code and parameters	101
5.3.2 Command descriptions	104
5.3.3 Error posting	247
5.4 Command Protocol	249
5.4.1 Non-data command protocol	250
5.4.2 PIO data-in command protocol	252
5.4.3 PIO data-out command protocol	254
5.4.4 DMA data-in command protocol	256
5.4.5 DMA data-out command protocol	257
5.4.6 Native Command Queuing protocol	258
5.5 Power-on and COMRESET	261
CHAPTER 6 Operations	263
6.1 Reset and Diagnosis	264
6.1.1 Response to power-on	264
6.1.2 Response to COMRESET	266
6.1.3 Response to a software reset	269
6.2 Power Save	270
6.2.1 Power save mode	270
6.2.2 Power commands	272
6.3 Power Save Controlled by Interface Power Management (IPM)	273
6.3.1 Power save mode of the interface	273
6.4 Read-ahead Cache	275
6.4.1 Data buffer structure	275
6.4.2 Caching operation	276
6.4.3 Using the read segment buffer	278
6.5 Write Cache	282
6.5.1 Cache operation	282
CHAPTER 7 Maintenance and Diagnosis	285
7.1 Maintenance	286
7.1.1 Rules for maintenance	286
7.1.2 Maintenance requirements	287
7.1.3 Maintenance levels	289
7.1.4 Disk drive revision number	290
7.1.5 Tools and test equipment	292
7.1.6 Self-diagnostics	292
7.1.7 Test	292
7.2 Operation Confirmation	295
7.2.1 Operation test	295
7.2.2 Diagnostic test	295
7.3 Troubleshooting Procedure	296
7.3.1 Troubleshooting procedure	296
7.3.2 Troubleshooting disk drive replaced in field	296
7.3.3 Troubleshooting at factory	298
7.4 Disk Drive Removal Procedure	299
7.5 Spare Disk Drive	299
Glossary	301
Acronyms and Abbreviations	305
Index	307
Comment Form	315

Match case Limit results 1 per page

4.6

Read/write Circuit

4.6.3

Read circuit

The head read signal from the PreAMP is regulated by the automatic gain control

(AGC) circuit.

Then the output is converted into the sampled read data pulse by

the programmable filter circuit and the flash digitizer circuit.

This signal is

converted into the read data by the decoder circuit based on the read data

maximum-likelihood-detected by the Viterbi detection circuit.

(1) AGC circuit

The AGC circuit automatically regulates the output amplitude to a constant value

even when the input amplitude level fluctuates.

The AGC amplifier output is

maintained at a constant level even when the head output fluctuates due to the

head characteristics or outer/inner head positions.

(2) Programmable filter circuit

The programmable filter circuit has a low-pass filter function that eliminates

unnecessary high frequency noise component and a high frequency boost-up

function that equalizes the waveform of the read signal.

Cut-off frequency of the low-pass filter and boost-up gain are controlled from the

The MPU optimizes the cut-off frequency and

boost-up gain according to the transfer frequency of each zone.

(3) FIR circuit

This circuit is 10-tap sampled analog transversal filter circuit that equalizes the

head read signal to the Modified Extended Partial Response (MEEPR) waveform.

(4) A/D converter circuit

This circuit changes Sampled Read Data Pulse from the FIR circuit into Digital

Read Data.

(5) Viterbi detection circuit

The sample hold waveform output from the flash digitizer circuit is sent to the

Viterbi detection circuit.

The Viterbi detection circuit demodulates data according

to the survivor path sequence.

4.6.4

Digital PLL circuit

The drive uses constant density recording to increase total capacity.

This is

different from the conventional method of recording data with a fixed data transfer

rate at all data area.

In the constant density recording method, data area is divided

into zones by radius and the data transfer rate is set so that the recording density of

the inner cylinder of each zone is nearly constant.

The drive divides data area into

30 zones to set the data transfer rate.

The MPU set the data transfer rate setup data (SD/SC) to the RDC block that

includes the Digital PLL circuit to change the data transfer rate.

C141-E293

4-11