HP ProLiant DL288 HP Power Regulator for ProLiant servers - Page 5

management feature. For this mode, system administrators must configure the operating system to activate the OS-based power management feature. If the operating system does not support dynamic power management, or if the feature has not been configured through the operating system, the processor will always run in its highest power and performance state. NOTE: Some earlier ProLiant servers refer to this option as Power Regulator Disabled. Power Regulator and Dynamic Power Savings In Dynamic Power Savings mode, Power Regulator determines the amount of time each processor in the system is spending in the operating system's idle loop. When the ratio of time spent in the idle loop to the time performing useful work is high, the algorithm instructs the processor to set its power state to Pmin (the lowest power and performance mode of the processor). Conversely, when the algorithm detects a low ratio indicating a high application load, the processor is switched in real time to Pmax, (the highest power and performance mode of the processor). Each processor in a system is monitored and adjusted independently. Dynamic Power Savings mode allows the processors to operate in a low power state when high processor performance is not needed and in a high power state when high processor performance is needed. Many customers find benefit in simply enabling the Dynamic Power Savings mode and allowing it to run continuously. When in HP Dynamic Power Savings mode, the Power Regulator algorithm continuously monitors application and processor loading up to eight times a second and adjusts the P-state accordingly. This continuous monitoring results in optimized P-state transitions. Measuring CPU utilization CPU utilization is determined by reading a performance event counter residing within the processor that is programmed to collect NON-HALTED clock cycles. This is an important event to harvest because modern operating systems execute a HLT instruction when idle, instead of spinning in an idle loop looking for work to do. Executing the HLT instruction during idle automatically brings the processor down to a low-power state, and stops incrementing the event counter of NON-HALTED clocks. The event counter is programmed to count kernel and user mode NON-HALTED clock cycles to properly account for processor utilization attributed to system software. Therefore, all processor activity (kernel-mode and user-mode) is accounted for in making power-state decisions. An interrupt pulls the processor out of the HLT instruction and restores the previous power state. Processor granularity The ROM-based dynamic power algorithm executes on a per-core basis, regardless of processor socket. More specifically it executes on every logical processor, including each core and hyperthread, and makes requests of the processor hardware to set the P-state of each logical processor based on its current utilization. However, the physical processors may require that some or all logical processors within the processor package be at the same P-state. As a result, while the power algorithm only requests the higher P-state for logical processors that require it, other logical processors within the same physical processor may be made to run at the higher P-state due to these architectural dependencies. This approach also ensures that no process running on the system has its performance adversely affected by the setting of a low P-state on a different logical processor. 5