Intel DP67BG Product Specification - Page 19

Intel, P67 Express Chipset

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Product Description 1.6 Intel® P67 Express Chipset The Intel P67 Express Chipset consisting of the Intel P67 Platform Controller Hub (PCH) provides interfaces to the processor and the USB, SATA, LAN, PCI, and PCIe interfaces. The PCH is a centralized controller for the board's I/O paths. For information about The Intel P67 Express Chipset Resources used by the chipset Refer to http://www.intel.com/products/desktop/chipsets/index.htm Chapter 2 1.6.1 USB The board supports up to 14 USB 2.0 ports and two USB 3.0 ports. The Intel P67 Express Chipset provides the USB controller for the 2.0 ports. The two USB 3.0 ports are provided by the NEC* UPD720200 controller. The port arrangement is as follows: • Two USB 3.0 ports are implemented with stacked back panel connectors (blue) • Eight USB 2.0 ports are implemented with stacked back panel connectors (black) • Six USB 2.0 front panel ports implemented through four internal headers All 16 USB ports are high-speed, full-speed, and low-speed capable. The USB 3.0 ports are super-speed capable. NOTES Computer systems that have an unshielded cable attached to a USB port may not meet FCC Class B requirements, even if no device is attached to the cable. Use a shielded cable that meets the requirements for full-speed devices. For information about The location of the USB connectors on the back panel The location of the front panel USB headers Refer to Figure 10, page 42 Figure 11, page 43 1.6.2 SATA Interfaces The board provides six SATA connectors through the PCH and one eSATA connector through a Marvell controller, which support one device per connector: • Two internal SATA 6.0 Gb/s connectors (blue) • Four internal SATA 3.0 Gb/s connectors (black) • One eSATA 3.0 Gb/s connector on the back panel for external connectivity (red) The PCH provides independent SATA ports with a theoretical maximum transfer rate of 6 Gb/s for two ports and 3 Gb/s for five ports. A point-to-point interface is used for host to device connections. The underlying SATA functionality is transparent to the operating system. The SATA controller can operate in both legacy and native modes. In legacy mode, standard IDE I/O and IRQ resources are assigned (IRQ 14 and 15). In Native mode, standard PCI 19

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Product Description
19
1.6
Intel
®
P67 Express Chipset
The Intel P67 Express Chipset consisting of the Intel P67 Platform Controller Hub
(PCH) provides interfaces to the processor and the USB, SATA, LAN, PCI, and PCIe
interfaces.
The PCH is a centralized controller for the board’s I/O paths.
For information about
Refer to
The Intel P67 Express Chipset
Resources used by the chipset
Chapter 2
1.6.1
USB
The board supports up to 14 USB 2.0 ports and two USB 3.0 ports.
The Intel P67 Express Chipset provides the USB controller for the 2.0 ports.
The two
USB 3.0 ports are provided by the NEC* UPD720200 controller.
The port arrangement
is as follows:
•
Two USB 3.0 ports are implemented with stacked back panel connectors (blue)
•
Eight USB 2.0 ports are implemented with stacked back panel connectors (black)
•
Six USB 2.0 front panel ports implemented through four internal headers
All 16 USB ports are high-speed, full-speed, and low-speed capable. The USB 3.0 ports
are super-speed capable.
NOTES
Computer systems that have an unshielded cable attached to a USB port may not
meet FCC Class B requirements, even if no device is attached to the cable.
Use a
shielded cable that meets the requirements for full-speed devices.
For information about
Refer to
The location of the USB connectors on the back panel
Figure 10, page 42
The location of the front panel USB headers
Figure 11, page 43
1.6.2
SATA Interfaces
The board provides six SATA connectors through the PCH and one eSATA connector
through a Marvell controller, which support one device per connector:
•
Two internal SATA 6.0 Gb/s connectors (blue)
•
Four internal SATA 3.0 Gb/s connectors (black)
•
One eSATA 3.0 Gb/s connector on the back panel for external connectivity (red)
The PCH provides independent SATA ports with a theoretical maximum transfer rate of
6 Gb/s for two ports and 3 Gb/s for five ports.
A point-to-point interface is used for
host to device connections.
The underlying SATA functionality is transparent to the operating system.
The SATA
controller can operate in both legacy and native modes.
In legacy mode, standard IDE
I/O and IRQ resources are assigned (IRQ 14 and 15).
In Native mode, standard PCI