Intel S815EBM1 Product Guide - Page 72

Table 33. I/O Map (continued) Address (hex) Size 96 contiguous bytes starting on a 128-byte divisible boundary 64 contiguous bytes starting on a 64-byte divisible boundary 64 contiguous bytes starting on a 64-byte divisible boundary 32 contiguous bytes starting on a 32-byte divisible boundary 32 contiguous bytes starting on a 32-byte divisible boundary 16 contiguous bytes starting on a 16-byte divisible boundary 4096 contiguous bytes starting on a 4096-byte divisible boundary Description ICH (ACPI + TCO) S815EBM1 board resource ICH2 LAN controller ICH2 USB controller #1 ICH2 USB controller #2 ICH2 (SMBus) Intel 82801BA PCI bridge * Default, but can be changed to another address range. ** Dword access only. *** Byte access only. Interrupts Table 34. Interrupts IRQ System Resource NMI I/O channel check 0 Reserved, interval timer 1 Reserved, keyboard buffer full 2 Reserved, cascade interrupt from slave PIC 3 User available 4 COM1* 5 LPT2 (Plug and Play option) user available 6 Diskette drive controller 7 LPT1* 8 Real time clock 9 User available 10 User available 11 User available 12 Onboard mouse port (if present, else user available) 13 Reserved, math coprocessor 14 Primary IDE (if present, else user available) 15 Secondary IDE (if present, else user available) * Default, but can be changed to another IRQ. 72 Intel Server Board S815EBM1 Product Guide