Intel X5472 Specification Update

Intel X5472 - Cpu Xeon Quad Core 3.00Ghz Fsb1600Mhz 12M Lga771 Tray Manual

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  • Intel X5472 | Specification Update - Page 1
    Intel® Xeon® Processor 5400 Series Specification Update December 2010 Document Number: 318585-019
  • Intel X5472 | Specification Update - Page 2
    will vary depending on the specific hardware and software you use. For more information including details on which processors support HT Technology, see here Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across
  • Intel X5472 | Specification Update - Page 3
    Content Revision History...5 Preface ...6 Summary Tables of Changes 8 Identification Information 15 Errata...18 Specification Changes 41 Specification Clarifications 42 Documentation Changes 43 § 3 Intel® Xeon® Processor 5400 Series Specification Update
  • Intel X5472 | Specification Update - Page 4
    Intel® Xeon® Processor 5400 Series 4 Specification Update
  • Intel X5472 | Specification Update - Page 5
    and AX66 Added Erratum AX67-AX70 Added Production E-step S-spec numbers to Table 1 Added Erratum AX71 Added Production E-step S-spec numbers to Table 1 Updated Erratum AX68 Added Erratum 2009 May 2009 June 2009 December 2010 December 2010 5 Intel® Xeon® Processor 5400 Series Specification Update
  • Intel X5472 | Specification Update - Page 6
    's Manual Documentation Changes Document Number/ Location http://www.intel.com/ design/processor/ applnots/241618.htm http://www.intel.com/ products/processor/ manuals/index.htm http://www.intel.com/ design/processor/ specupdt/252046.htm Intel® Xeon® Processor 5400 Series 6 Specification Update
  • Intel X5472 | Specification Update - Page 7
    . Products are differentiated by their unique characteristics,e.g., core speed, L2 cache size, package type, etc. as described in the processor identification information table. Read all notes associated with each S-Spec number. Specification Changes are modifications to the current published
  • Intel X5472 | Specification Update - Page 8
    ® III processor F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor I = Intel® Xeon® processor 5000 series J = 64-bit Intel® Xeon® processor MP with 1MB L2 cache K = Mobile Intel® Pentium® III processor Intel® Xeon® Processor 5400 Series 8 Specification Update
  • Intel X5472 | Specification Update - Page 9
    ® Xeon® processor MP Intel ® Xeon® processor Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading Technology (Intel® HT Technology) on 90-nm process technology Intel® Pentium® 4 processor on 90 nm process 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache
  • Intel X5472 | Specification Update - Page 10
    ® processor E1000 series Intel® Core™ 2 extreme Processor OX9775 Intel® Atom™ Processor Z5xx series Intel® Atom™ Processor 200 series Intel® Atom™ Processor N series Intel® Atom™ Processor 300 series Intel® Xeon® Processor 7400 Series Intel® Xeon® Processor 5400 Series 10 Specification Update
  • Intel X5472 | Specification Update - Page 11
    L2 ECC Errors May be Incorrect AX18 X AX19 X AX20 X Code Segment Limit/Canonical Faults on RSM May be Serviced AX22 X X No Fix Performance Monitoring Events for Retired Instructions (C0H) May Not Be Accurate AX23 X AX24 X Intel® Xeon® Processor 5400 Series Specification Update
  • Intel X5472 | Specification Update - Page 12
    Processor Behavior X Fixed RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results X No Fix Benign Exception after a Double Fault May Not Cause a Triple Fault Shutdown Intel® Xeon® Processor 5400 Series 12 Specification
  • Intel X5472 | Specification Update - Page 13
    Page Faults May Set the RSVD Flag in the Error Code X No Fix VM Exits Due to "NMI-Window Exiting" May Be Delayed by One Instruction X No Fix A 64-bit Register IP-relative Instruction May Return Unexpected Results 13 Intel® Xeon® Processor 5400 Series Specification Update
  • Intel X5472 | Specification Update - Page 14
    this specification update. Specification Clarifications Number SPECIFICATION CLARIFICATIONS AX1 Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Documentation Changes Number DOCUMENTATION CHANGES None for this revision of this specification update. Intel® Xeon® Processor
  • Intel X5472 | Specification Update - Page 15
    . See Table 2 for the processor stepping ID number in the CPUID information. Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register. 15 Intel® Xeon® Processor 5400 Series Specification Update
  • Intel X5472 | Specification Update - Page 16
    S-Spec Processor Number Core Stepping CPUID1 Core Freq (GHz) SLANZ SLANP SLASA SLASB SLANR SLANQ SLANS SLANT SLANU SLANV SLANW SLAP2 SLAP5 SLAP4 SLARP SLBBD SLBBG SLBBF SLBBB SLBBA X5482 X5460 X5472 X5450 E5472 E5450 E5440 E5462 E5430 E5420 E5410 E5405 L5408 L5410 L5420 X5492 X5482 X5470 X5472
  • Intel X5472 | Specification Update - Page 17
    Table 1. Intel® Xeon® Processor 5400 Series Identification Information (Sheet 2 of 2) Processor Core S-Spec Number Stepping CPUID1 Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size (MB) Thermal Design Power (TDP) Notes SLBBE X5450 E-0 1067Ah 3 1333 12 (2x6MB) 120 SLBBH E5472 E-0
  • Intel X5472 | Specification Update - Page 18
    May be Incomplete under Certain Conditions Problem: The INVLPG instruction may not completely invalidate Translation Look-aside may get the data from external memory or L2 written by another core, while the second load will get the data Intel® Xeon® Processor 5400 Series 18 Specification Update
  • Intel X5472 | Specification Update - Page 19
    . Problem: Storage of PEBS Record Delayed Following Execution of MOV SS or STI When a performance monitoring counter is configured for PEBS (Precise Event Based Sampling), overflow of the counter results in storage of a PEBS record in the PEBS 19 Intel® Xeon® Processor 5400 Series Specification
  • Intel X5472 | Specification Update - Page 20
    of the Monitoring Hardware Problem: The MONITOR instruction is used to arm the address monitoring hardware for the subsequent MWAIT instruction. The hardware is triggered the steppings affected, see the Summary Tables of Changes. Intel® Xeon® Processor 5400 Series 20 Specification Update
  • Intel X5472 | Specification Update - Page 21
    Sometimes May Appear to Have Not Occurred Problem: With respect to the retirement of instructions, stores to the uncacheable memorybased APIC Manual section "Outof-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family 21 Intel® Xeon® Processor 5400 Series Specification
  • Intel X5472 | Specification Update - Page 22
    single REP MOVS or REP STOS instruction that will execute with fast strings L2 ECC Errors May be Incorrect Problem: When correctable Single-bit ECC errors occur in the L2 cache #GP fault may be serviced before a higher priority Interrupt Intel® Xeon® Processor 5400 Series 22 Specification Update
  • Intel X5472 | Specification Update - Page 23
    serviced before higher priority Interrupts and Exceptions. Intel Problem: According to Intel® 64 and IA-32 Intel Architecture Software Developer's Manual, Volume 3A "Methods of Caching effect, restarting the instruction may cause unexpected Intel® Xeon® Processor 5400 Series Specification Update
  • Intel X5472 | Specification Update - Page 24
    for Retired Instructions (C0H) May Not Be Accurate Problem: The INST_RETIRED performance monitor may miscount retired instructions as no Interrupt Service Routine (ISR) set up for that vector the system will GP fault. If the ISR does Intel® Xeon® Processor 5400 Series 24 Specification Update
  • Intel X5472 | Specification Update - Page 25
    Serviced Before Higher Priority Interrupts Problem: Interrupts that are pending prior to the execution of the STI (Set Interrupt Flag) instruction are normally serviced immediately after the instruction left in TLB after INIT. 25 Intel® Xeon® Processor 5400 Series Specification Update
  • Intel X5472 | Specification Update - Page 26
    cache lines within the monitored address range. Implication: The logical processor that executed the MWAIT instruction may Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Problem: Software Intel® Xeon® Processor 5400 Series 26 Specification Update
  • Intel X5472 | Specification Update - Page 27
    : B0-B3 bits in DR6 may not be properly cleared. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 27 Intel® Xeon® Processor 5400 Series Specification Update
  • Intel X5472 | Specification Update - Page 28
    event that causes instruction restart will be expecting this instruction to still be in the fetch unit and lack of it will cause a system hang or an MCE. This erratum has not been observed with commercially available software. Intel® Xeon® Processor 5400 Series 28 Specification Update
  • Intel X5472 | Specification Update - Page 29
    Problem: Under certain conditions, as described in the Software Developers Manual section "Out- of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors", the processor type to a cache line previously written by a preceding fast string/FXSAVE instruction may be
  • Intel X5472 | Specification Update - Page 30
    Not Be Blocked by a VM-Entry Failure Problem: The Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2 specifies that, following a VM- affected, see the Summary Tables of Changes. Intel® Xeon® Processor 5400 Series 30 Specification Update
  • Intel X5472 | Specification Update - Page 31
    TLB (Translation Lookaside Buffers) and paging-structures caches in the processor, in conjunction with a complex sequence of internal processor micro-architectural events and store operations, may lead to unexpected processor behavior. 31 Intel® Xeon® Processor 5400 Series Specification Update
  • Intel X5472 | Specification Update - Page 32
    AX49. RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results Problem: Problem: RSM instruction execution, under the steppings affected, see the Summary Tables of Changes. Intel® Xeon® Processor 5400 Series 32 Specification Update
  • Intel X5472 | Specification Update - Page 33
    Instruction if it is Followed by an Instruction That Signals a Floating Point Exception Problem: A MOV SS/POP SS instruction IA-32 Intel® Architecture Software Developer's Manual, the Specifically, information about the software interrupt 33 Intel® Xeon® Processor 5400 Series Specification Update
  • Intel X5472 | Specification Update - Page 34
    During or After Loading Guest State" of Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2. (The exit reason will be 80000021H and the exit qualification will be zero.) Note that the Intel® Xeon® Processor 5400 Series 34 Specification Update
  • Intel X5472 | Specification Update - Page 35
    For the steppings affected, see the Summary Tables of Changes. AX59. Problem: VM Entry May Use Wrong Address to Access Virtual-APIC Page When , the instruction TLB (Translation Lookaside Buffer) entries caching global page translations 35 Intel® Xeon® Processor 5400 Series Specification Update
  • Intel X5472 | Specification Update - Page 36
    follows the write to CR0 to enable protected mode. Intel has not observed this erratum with any commercially available software. Workaround: None Identified Status: For the steppings affected, see the Summary Tables of Changes. Intel® Xeon® Processor 5400 Series 36 Specification Update
  • Intel X5472 | Specification Update - Page 37
    Changes. AX68. Problem: The XSAVE Instruction May Erroneously Modify processor context in the XSAVE instruction flow, when XSAVE is used to store only the SSE context, may appear to execute before the completion of older store operations. 37 Intel® Xeon® Processor 5400 Series Specification
  • Intel X5472 | Specification Update - Page 38
    Operations Can Cause Unexpected Instruction Execution Results Problem: The act of one processor, or system bus Intel Architecture Software Developer's Manual Volume 3: System Programming Guide, Section: Handling Self- and Cross-Modifying Code. Intel® Xeon® Processor 5400 Series 38 Specification
  • Intel X5472 | Specification Update - Page 39
    PDPTE Problem: On processors supporting Intel® 64 instruction result may be incorrect and could cause software to read from or write to an incorrect memory location. This may result in an unexpected page fault or unpredictable system behavior. 39 Intel® Xeon® Processor 5400 Series Specification
  • Intel X5472 | Specification Update - Page 40
    Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the "Summary Tables of Changes". Intel® Xeon® Processor 5400 Series 40 Specification Update
  • Intel X5472 | Specification Update - Page 41
    Specification Changes The Specification Changes listed in this section apply to the following documents: • Intel® Xeon® Processor 5400 Series Datasheet There are no new Specification Changes in this Specification Update revision. 41 Intel® Xeon® Processor 5400 Series Specification Update
  • Intel X5472 | Specification Update - Page 42
    AX1. Issue: The Specification Clarifications listed in this section may apply to the following documents: • Intel® Xeon® Processor 5400 Series Datasheet. • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide. Clarification of TRANSLATION LOOKASIDE
  • Intel X5472 | Specification Update - Page 43
    Software Developer's Manual Documentation Changes. Follow the link below to become familiar with this file. http://developer.intel.com/products/processor/manuals/index.htm There are no new Documentation Changes in this Specification Update revision. § 43 Intel® Xeon® Processor 5400 Series
  • Intel X5472 | Specification Update - Page 44
    Intel® Xeon® Processor 5400 Series 44 Specification Update
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Document Number: 318585-019
Intel® Xeon® Processor 5400 Series
Specification Update
December 2010