Intel X5472 Specification Update - Page 11

Errata Intel® Xeon® Processor 5400 Series (Sheet 1 of 3) Number Stepping Stepping C-0 E-0 Status (Hardware Fix?) ERRATA AX1 X X No Fix EFLAGS Discrepancy on Page Faults After a Translation Change AX2 X X No Fix INVLPG Operation for Large (2M/4M) Pages May be Incomplete under Certain Conditions AX3 X AX4 X AX5 X X No Fix Store to WT Memory Data May be Seen in Wrong Order by Two Subsequent Loads X No Fix Non-Temporal Data Store May be Observed in Wrong Program Order X No Fix Page Access Bit May be Set Prior to Signaling a Code Segment Limit Fault AX6 X AX7 X X No Fix Updating Code Page Directory Attributes without TLB Invalidation May Result in Improper Handling of Code #PF X No Fix Storage of PEBS Record Delayed Following Execution of MOV SS or STI AX8 X X No Fix Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions AX9 X AX10 X AX11 X AX12 X AX13 X AX14 X X No Fix A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware X No Fix Performance Monitoring Event MISALIGN_MEM_REF May Over Count X No Fix The Processor May Report a #TS Instead of a #GP Fault X No Fix Code Segment Limit Violation May Occur on 4 Gigabyte Limit Check X No Fix A Write to an APIC Register Sometimes May Appear to Have Not Occurred X No Fix Last Branch Records (LBR) Updates May be Incorrect after a Task Switch AX15 X REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page X No Fix Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering Violations. AX16 X X No Fix Upper 32 bits of 'From' Address Reported through BTMs or BTSs May be Incorrect AX17 X X No Fix Address Reported by Machine-Check Architecture (MCA) on Single-bit L2 ECC Errors May be Incorrect AX18 X AX19 X AX20 X Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher X No Fix Priority Interrupts/Exceptions and May Push the Wrong Address Onto the Stack X No Fix Store Ordering May be Incorrect between WC and WP Memory Type X No Fix EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after Shutdown AX21 X X No Fix Premature Execution of a Load Operation Prior to Exception Handler Invocation AX22 X X No Fix Performance Monitoring Events for Retired Instructions (C0H) May Not Be Accurate AX23 X AX24 X X No Fix Returning to Real Mode from SMM with EFLAGS.VM Set May Result in Unpredictable System Behavior X No Fix CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal to 248 May Terminate Early AX25 X X No Fix Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt 11 Intel® Xeon® Processor 5400 Series Specification Update