Intel X5472 Specification Update - Page 12

Errata Intel® Xeon® Processor 5400 Series (Sheet 2 of 3) Number Stepping Stepping C-0 E-0 Status (Hardware Fix?) ERRATA AX26 X AX27 X AX28 X AX29 X AX30 X AX31 X AX32 X AX33 X AX34 X AX35 X AX36 X AX37 X AX38 X AX39 X AX40 X AX41 X AX42 X AX43 X AX44 X AX45 X AX46 X AX47 X AX48 X AX49 X AX50 X X No Fix Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced Before Higher Priority Interrupts X No Fix VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (LER) MSR X No Fix INIT Does Not Clear Global Entries in the TLB X No Fix Split Locked Stores May not Trigger the Monitoring Hardware X No Fix Programming the Digital Thermal Sensor (DTS) Threshold May Cause Unexpected Thermal Interrupts X No Fix Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue X No Fix General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit Violation above 4-G Limit X No Fix An Asynchronous MCE During a Far Transfer May Corrupt ESP X Plan Fix CPUID Reports Architectural Performance Monitoring Version 2 is Supported, When Only Version 1 Capabilities are Available X No Fix B0-B3 Bits in DR6 May Not be Properly Cleared After Code Breakpoint X No Fix An xTPR Update Transaction Cycle, if Enabled, May be Issued to the FSB after the Processor has Issued a Stop-Grant Special Cycle Fixed Performance Monitoring Event IA32_FIXED_CTR2 May Not Function Properly when Max Ratio is a Non-Integer Core-to-Bus Ratio X No Fix Instruction Fetch May Cause a Livelock During Snoops of the L1 Data Cache X No Fix Use of Memory Aliasing with Inconsistent Memory Type may Cause a System Hang or a Machine Check Exception X No Fix A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to MemoryOrdering Violations Fixed VM Exit with Exit Reason "TPR Below Threshold" Can Cause the Blocking by MOV/POP SS and Blocking by STI Bits to be Cleared in the Guest Interruptability-State Field X No Fix Using Memory Type Aliasing with Cacheable and WC Memory Types May Lead to Memory Ordering Violations X No Fix VM Exit Caused by a SIPI Results in Zero Being Saved to the Guest RIP Field in the VMCS Fixed NMIs May Not Be Blocked by a VM-Entry Failure Fixed Partial Streaming Load Instruction Sequence May Cause the Processor to Hang X Not Fixed Self/Cross Modifying Code May Not be Detected or May Cause a Machine Check Exception Fixed Data TLB Eviction Condition in the Middle of a Cacheline Split Load Operation May Cause the Processor to Hang Fixed Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor Behavior X Fixed RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results X No Fix Benign Exception after a Double Fault May Not Cause a Triple Fault Shutdown Intel® Xeon® Processor 5400 Series 12 Specification Update