Intel X5472 Specification Update - Page 39

Status: For the steppings affected, see the "Summary Tables of Changes". AX73. A Page Fault May Not be Generated When the PS bit is set to "1" in a PML4E or PDPTE Problem: On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7) is reserved in PML4Es and PDPTEs. If the translation of the linear address of a memory access encounters a PML4E or a PDPTE with PS set to 1, a page fault should occur. Due to this erratum, PS of such an entry is ignored and no page fault will occur due to its being set. Implication: Software may not operate properly if it relies on the processor to deliver page faults when reserved bits are set in paging-structure entries. Workaround: Software should not set bit 7 in any PML4E or PDPTE that has Present Bit (Bit 0) set to "1". Status: For the steppings affected, see the "Summary Tables of Changes". AX74. Not-Present Page Faults May Set the RSVD Flag in the Error Code Problem: An attempt to access a page that is not marked present causes a page fault. Such a page fault delivers an error code in which both the P flag (bit 0) and the RSVD flag (bit 3) are 0. Due to this erratum, not-present page faults may deliver an error code in which the P flag is 0 but the RSVD flag is 1. Implication: Software may erroneously infer that a page fault was due to a reserved-bit violation when it was actually due to an attempt to access a not-present page. Intel has not observed this erratum with any commercially available software. Workaround: Page-fault handlers should ignore the RSVD flag in the error code if the P flag is 0. Status: For the steppings affected, see the "Summary Tables of Changes" AX75. VM Exits Due to "NMI-Window Exiting" May Be Delayed by One Instruction Problem: If VM entry is executed with the "NMI-window exiting" VM-execution control set to 1, a VM exit with exit reason "NMI window" should occur before execution of any instruction if there is no virtual-NMI blocking, no blocking of events by MOV SS, and no blocking of events by STI. If VM entry is made with no virtual-NMI blocking but with blocking of events by either MOV SS or STI, such a VM exit should occur after execution of one instruction in VMX non-root operation. Due to this erratum, the VM exit may be delayed by one additional instruction. Implication: VMM software using "NMI-window exiting" for NMI virtualization should generally be unaffected, as the erratum causes at most a one-instruction delay in the injection of a virtual NMI, which is virtually asynchronous. The erratum may affect VMMs relying on deterministic delivery of the affected VM exits. Workaround: None Identified. Status: For the steppings affected, see the "Summary Tables of Changes". AX76. Problem: Implication: A 64-bit Register IP-relative Instruction May Return Unexpected Results Under an unlikely and complex sequence of conditions in 64-bit mode, a register IPrelative instruciton result may be incorrect. A register IP-relative instruction result may be incorrect and could cause software to read from or write to an incorrect memory location. This may result in an unexpected page fault or unpredictable system behavior. 39 Intel® Xeon® Processor 5400 Series Specification Update