Sony HCD-HX7 Service Manual - Page 54

Pin No., Pin Name, Description

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Page 54 highlights

HCD-HX3/HX5/HX7 Pin No. 44 45 46 47 48 49, 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 Pin Name TEST IRQ AoUT3 (PO4) AoUT2 (PO5) PIO0 PIO1, PIO2 PIO3 VSS1 VDDT3 SBSY SBOK/FOK IPF SFSY/LOCK ZDET GPIN MS DOUT (PO6) AOUT (PO7) BCK (PO8) LRCK (PO9) AIN (PI4) BCKi (PI5) LRCKi (PI6) VDD1 VSS AWRC PVDD3 PDO TMAXS TMAX LPFN LPFo PVREF VCOF PVSS3 SLCo RFi RFRPi RFEQo VRo RESiN VMDiR TESTR AGCi RFo RVDD3 I/O Description I Setting terminal for test mode Normally fixed at "L" I Interrupt request signal input terminal Not used O Request signal output to the USB controller (HX3/HX5) O Audio data output terminal Not used O Request signal output to the system controller and USB controller (HX3/HX5) Request signal output to the system controller (HX7) O Not used I Gate signal input from the USB controller (HX3/HX5) - Ground terminal - Power supply terminal (+3.3 V) O Subcode block sync signal output to the system controller O Not used O Not used O Not used O Zero detection signal output terminal Not used I Not used I Microcomputer interface mode selection signal input terminal Fixed at "H" in this set O Digital audio data output terminal Not used O Audio data output terminal Not used O Bit clock signal output terminal Not used O L/R sampling clock signal output terminal Not used I Digital audio data input from USB controller (HX3/HX5) I Bit clock signal input from the USB controller (HX3/HX5) I L/R sampling clock signal input from the USB controller (HX3/HX5) - Power supply terminal (+1.5 V) - Ground terminal - Not used - Power supply terminal (+3.3 V) O Phase error margin signal between EFM signal and PLCK signal output terminal O TMAX detection signal output terminal Not used O TMAX detection signal output terminal I Inverted signal input from the operation amplifier for PLL loop filter O Signal output from the operation amplifier for PLL loop filter I Reference voltage (+1.65V) input terminal O VCO filter output terminal - Ground terminal O EFM slice level output terminal I RF signal input terminal I RF ripple signal input terminal O EFM slice level output terminal O Reference voltage (+1.65V) output terminal O External resistor connection terminal O Reference voltage (+1.65V) output terminal for automatic power control circuit O Low-pass filter terminal for RFEQO offset correction I RF signal amplitude adjustment amplification input terminal O RF signal generation amplification output terminal - Power supply terminal (+3.3 V) 54

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54
HCD-HX3/HX5/HX7
Pin No.
Pin Name
I/O
Description
44
TEST
I
Setting terminal for test mode
Normally fixed at "L"
45
IRQ
I
Interrupt request signal input terminal
Not used
46
AoUT3 (PO4)
O
Request signal output to the USB controller (HX3/HX5)
47
AoUT2 (PO5)
O
Audio data output terminal
Not used
48
PIO0
O
Request signal output to the system controller and USB controller (HX3/HX5)
Request signal output to the system controller (HX7)
49, 50
PIO1, PIO2
O
Not used
51
PIO3
I
Gate signal input from the USB controller (HX3/HX5)
52
VSS1
-
Ground terminal
53
VDDT3
-
Power supply terminal (+3.3 V)
54
SBSY
O
Subcode block sync signal output to the system controller
55
SBOK/FOK
O
Not used
56
IPF
O
Not used
57
SFSY/LOCK
O
Not used
58
ZDET
O
Zero detection signal output terminal
Not used
59
GPIN
I
Not used
60
MS
I
Microcomputer interface mode selection signal input terminal
Fixed at "H" in this set
61
DOUT (PO6)
O
Digital audio data output terminal
Not used
62
AOUT (PO7)
O
Audio data output terminal
Not used
63
BCK (PO8)
O
Bit clock signal output terminal
Not used
64
LRCK (PO9)
O
L/R sampling clock signal output terminal
Not used
65
AIN (PI4)
I
Digital audio data input from USB controller (HX3/HX5)
66
BCKi (PI5)
I
Bit clock signal input from the USB controller (HX3/HX5)
67
LRCKi (PI6)
I
L/R sampling clock signal input from the USB controller (HX3/HX5)
68
VDD1
-
Power supply terminal (+1.5 V)
69
VSS
-
Ground terminal
70
AWRC
-
Not used
71
PVDD3
-
Power supply terminal (+3.3 V)
72
PDO
O
Phase error margin signal between EFM signal and PLCK signal output terminal
73
TMAXS
O
TMAX detection signal output terminal
Not used
74
TMAX
O
TMAX detection signal output terminal
75
LPFN
I
Inverted signal input from the operation amplifier for PLL loop filter
76
LPFo
O
Signal output from the operation amplifier for PLL loop filter
77
PVREF
I
Reference voltage (+1.65V) input terminal
78
VCOF
O
VCO filter output terminal
79
PVSS3
-
Ground terminal
80
SLCo
O
EFM slice level output terminal
81
RFi
I
RF signal input terminal
82
RFRPi
I
RF ripple signal input terminal
83
RFEQo
O
EFM slice level output terminal
84
VRo
O
Reference voltage (+1.65V) output terminal
85
RESiN
O
External resistor connection terminal
86
VMDiR
O
Reference voltage (+1.65V) output terminal for automatic power control circuit
87
TESTR
O
Low-pass filter terminal for RFEQO offset correction
88
AGCi
I
RF signal amplitude adjustment amplification input terminal
89
RFo
O
RF signal generation amplification output terminal
90
RVDD3
-
Power supply terminal (+3.3 V)