Via EPIA-EK10000G User Manual - Page 67
DRAM Clock, DRAM Timing
UPC - 825529003581
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FREQUENCY / VOLTAGE CONTROL BIOS Setup Phoenix - AwardBIOS CMOS Setup Utility Frequency / Voltage Control DRAM Clock DRAM Timing SDRAM CAS Latency Bank Interleave Precharge to Active(Trp) Active to Precharge(Tras) Active to CMD(Trcd) REF to ACT/REF to REF(Trfc ACT(0) to ACT(1) (TRRD) DRAM Command Rate Spread Spectrum Range [By SPD] [Auto By SPD] 2.5 Disabled 4T 9T 4T 15T 3T [2T Command] [+/- 0.3%] Item Help Menu Level Spread Spectrum [Enabled] : Move Enter: Select +/-/PU/PD: Value F10: Save F5: Previous Values F6: Fail-Safe Defaults ESC: Exit F1: General Help F7: Optimized Defaults DRAM Clock The chipset supports synchronous and asynchronous mode between host clock and DRAM clock frequency. Settings: [100 MHz, 133 MHz, 166 MHz, 200MHz, By SPD] DRAM Timing The value in this field depends on the memory modules installed in your system. Changing the value from the factory setting is not recommended unless you install new memory that has a different performance rating than the original modules. Settings: [Manual, Auto By SPD] 59