ASRock Fatal1ty X299 Gaming K6 User Manual - Page 72

Change Pll Trim Prefix, Intel Speed Shift Technology

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SRCO Source Select CPU PLL or PCIE PLL as the SRCO source. ClockGen Delay Configure the delay at the beginning of Clockgen. ClockGen GPIO Configure the General-purpose input/output (GPIO) at the beginning of Clockgen. Boot Performance Mode Select the performance state that the BIOS will set before OS handoff. FCLK Frequency Configure the FCLK Frequency. Intel Turbo Boost Technology Intel Turbo Boost Technology enables the processor to run above its base operating frequency when the operating system requests the highest performance state. Intel SpeedStep Technology Intel SpeedStep technology allows processors to switch between multiple frequencies and voltage points for better power saving and heat dissipation. Intel Speed Shift Technology Enable/Disable Intel Speed Shift Technology support. Enabling will expose the CPPC v2 interface to allow for hardware controlled P-states. MFC Mode Override Configure the MFC Mode Override. Adjust Pll Adjust the Pll for higher -BCLK ration combination. Change Pll Trim Value Adjust the Pll value between +63 ro -63. Change Pll Trim Prefix Adjust the Pll Trim Prefix. Change MC-Pll Trim Value Adjust the MC-Pll value between +63 ro -63. 64 English

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English
64
SRCO Source
Select CPU PLL or PCIE PLL as the SRCO source.
ClockGen Delay
Configure the delay at the beginning of Clockgen.
ClockGen GPIO
Configure the General-purpose input/output (GPIO) at the beginning of Clockgen.
Boot Performance Mode
Select the performance state that the BIOS will set before OS handoff.
FCLK Frequency
Configure the FCLK Frequency.
Intel Turbo Boost Technology
Intel Turbo Boost Technology enables the processor to run above its base operating
frequency
when the operating system requests the highest performance state.
Intel SpeedStep Technology
Intel SpeedStep technology allows processors to switch between multiple frequen-
cies and voltage points for better power saving and heat dissipation.
Intel Speed Shift Technology
Enable/Disable Intel Speed Shiſt Technology support. Enabling will expose the
CPPC v2 interface to allow for hardware controlled P-states.
MFC Mode Override
Configure the MFC Mode Override.
Adjust Pll
Adjust the Pll for higher -BCLK ration combination.
Change Pll Trim Value
Adjust the Pll value between +63 ro -63.
Change Pll Trim Prefix
Adjust the Pll Trim Prefix.
Change MC-Pll Trim Value
Adjust the MC-Pll value between +63 ro -63.