ASRock K8S8X User Manual - Page 32

Memory Controller Configuration, 7.1.1, Memory Configuration

Page 32 highlights

3.7.1 Memory Controller Configuration In this section, it will display the status of memory clock, CAS Latency, TRCD, TRAS, and TRP. You may also set the memory configuration in the sub-screen under this section. BIOS SETUP UTILITY Memory Controller Configuration Memory Configuration Memory CLK CAS Latency TRCD TRAS TRP : 166 MHz : 3.0 : 4 CLK : 7 CLK : 4 CLK Chipset Select Screen Select Item Enter Go to Sub Screen F1 General Help F9 Load Defaults F10 Save and Exit ESC Exit v02.54 (C) Copyright 1985-2003, American Megatrends, Inc. 3.7.1.1 Memory Configuration BIOS SETUP UTILITY Memory Configuration Memory Clock Bank Interleaving Node Interleaving Burst Length CAS Latency (CL) TRCD TRAS TRP [Auto] [Auto] [Disabled] [8 Beats] [Auto] [Auto] [Auto] [Auto] Chipset Memory Clock can be set by the code using AUTO, or you can set one of the standard values. +F1 F9 F10 ESC Select Screen Select Item Change Option General Help Load Defaults Save and Exit Exit v02.54 (C) Copyright 1985-2003, American Megatrends, Inc. Memory Clock This item can be set by the code using [Auto]. You can set one of the standard values as listed: [100 MHz (DDR200)], [133 MHz (DDR266)], [166 MHz (DDR333)], [200 MHz (DDR400)]. Bank Interleaving Interleaving allows memory accesses to be spread out over banks on the same node, or accross nodes, decreasing access contention. 32

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32
3.7.1
Memory Controller Configuration
In this section, it will display the status of memory clock, CAS Latency, TRCD,
TRAS, and TRP. You may also set the memory configuration in the sub-screen
under this section.
3.7.1.1
Memory Configuration
Memory Clock
This item can be set by the code using [Auto]. You can set one of the
standard values as listed: [100 MHz (DDR200)], [133 MHz (DDR266)], [166
MHz (DDR333)], [200 MHz (DDR400)].
Bank Interleaving
Interleaving allows memory accesses to be spread out over banks on the
same node, or accross nodes, decreasing access contention.
BIOS SETUP UTILITY
Select Screen
Select Item
Enter
Go to Sub Screen
F1
General Help
F10
Save and Exit
ESC
Exit
F9
Load Defaults
v02.54 (C) Copyright 1985-2003, American Megatrends, Inc.
Chipset
Memory Controller Configuration
Memory Configuration
Memory CLK
CAS Latency
TRCD
TRAS
TRP
: 166 MHz
: 3.0
: 4 CLK
: 7 CLK
: 4 CLK
BIOS SETUP UTILITY
v02.54 (C) Copyright 1985-2003, American Megatrends, Inc.
Chipset
Memory Configuration
Memory Clock
Bank Interleaving
Node Interleaving
Burst Length
CAS Latency (CL)
TRCD
TRAS
TRP
[Auto]
[Disabled]
[8 Beats]
[Auto]
[Auto]
[Auto]
[Auto]
[Auto]
Memory Clock can be
set by the code using
AUTO, or you can set
one of the standard
values.
Select Screen
Select Item
+-
Change Option
F1
General Help
F10
Save and Exit
ESC
Exit
F9
Load Defaults