Acer Aspire 4743Z Aspire 4743 and 4743Z Notebook Series Service Guide - Page 200

POST Codes 0 The following table details the core POST codes and functions used in SecureCore. Table 4-4. POST Codes POST Code Function 0xE3 First Legacy BIOS Task table for legacy reset Phase Component LBT Core 0x20 Verify that DRAM refresh is operating by polling the refresh LBT bit in PORTB. Core 0xDA Dummy PCIE Init entry, now handled by driver LBT Core 0x29 PMM (Post Memory Manager) Init LBT Core 0xE5 WHEA Init LBT Core 0x33 PDM (Post Dispatcher Manager) Init LBT Core 0x01 IPMI Init LBT Core 0xD8 ASF Init LBT Core 0x09 Set in-POST flag in CMOS that indicates we are in POST. LBT If this bit is cleared by postClearBootFlagJ (AEh), the TrustedCore on next boot determines that the current configuration caused POST to fail and uses default values for configuration. Core 0x2B Enhanced CMOS LBT Core 0XE0 EFI Variable Init LBT Core 0xC1 PEM (Post Error Manager) Init LBT Core 0x3B Debug Service Init (ROM Polit) LBT Core 0xDC POST Update Error LBT Core 0x3A Autosize external cache and program cache size for enabling later in POST. LBT Core 0x0B Enable CPU cache. Set bits in CMOS related to cache. LBT Core 0x0F Enable the local bus IDE as primary or secondary LBT Core 0x10 Initialize Power Management LBT Core 0x14 Verify that the 8742 keyboard controller is responding. LBT Send a self-test command to the 8742 and wait for results. Also read the switch inputs from the 8742 and write the keyboard controller command byte. Core 4-26 Troubleshooting