Acer Aspire 4743Z Aspire 4743 and 4743Z Notebook Series Service Guide - Page 203

Table 4-4. POST Codes POST Code Function Phase Component 0xC9 pretask before EISA init LBT Core 0x51 EISA Init LBT Core 0x5A Display prompt "Press F2 to enter SETUP" LBT Core 0x5B Disable CPU cache. LBT Core 0x5C Test RAM between 512K and 640K. LBT Core 0x60 Determine and test the amount of extended memory LBT available. Determine if memory exists by writing to a few strategic locations and see if the data can be read back. If so, perform an address-line test and a RAM test on the memory. Save the total extended Core 0x62 The amount of memory available. This test is dependent LBT on the processor, since the test will vary depending on the width of memory (16 or 32 bits). This test will also use A20 as the skew address to prevent corruption of the system memory. Core 0x64 Jump to UserPatch1. LBT Core 0x66 Set cache registers to their CMOS values if CMOS is valid, LBT unless auto configuration is enabled, in which case load cache registers from the Setup default table. Core 0x68 Enable external cache and CPU cache if present. Configure non-cacheable regions if necessary. LBT Core 0x6A Display external cache size on the screen if it is non-zero. LBT Core 0x6C Display shadow message LBT Core 0xCA Post EISA init LBT Core 0x70 Check flags in CMOS and in the TrustedCore data area for LBT errors detected during POST. Display error messages on the screen. Core 0x72 Check status bits to see if configuration problems were detected. If so, display error messages on the screen. LBT Core 0x4F Initialize MultiBoot. Allocate memory for old and new MultiBoot history tables. LBT Core 0xCD Reclaim console vector after HW vectors initialized. LBT Core 0x7D Initialize Intelligent System Monitoring. LBT Core 0x7E The Coprocessor initialization test. Use the floating point LBT instructions to determine if a coprocessor exists instead of the ET bit in CR0. Core 0xC1 Check Boot Type (Server BIOS) LBT Core 0x80 Disable onboard COM and LPT ports before testing for presence of external I/O devices. LBT Core Troubleshooting 4-29