Asus ROG MAXIMUS Z790 DARK HERO ROG Z790 Series BIOS Manual English - Page 52

PCIE/DMI Spread Spectrum, PCIE/DMI Slew Rate

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BCLK Slew Rate Allows you set the speed at which the base clock rises or falls. Set a high value for overclocking stability. Configuration options: [Auto] [Slow] [Fast] BCLK Spread Spectrum Allows you to reduce the EMI. Disable to get more accurate base clocks. Configuration options: [Auto] [Disabled] [Enabled] Initial PCIE Frequency Allows setting a different PCIE BCLK value during POST. May be useful for setting a lower PCIE BCLK in scenarios where memory training is not stable at a higher BCLK (a large frequency gap between BCLK Frequency and Initial frequency is not recommended). Applies same value as BCLK Frequency if left at default. Use the and keys to adjust the value. The values range from 80.000MHz to 200.000MHz with an interval of 0.100MHz. Configuration options: [Auto] [80.0000] - [200.00000] PCIE/DMI Amplitude Allows you to set the signal magnitude of the reference PCIE/DMI CLK supplied to the processor. Higher values may improve overclocking stability. Configuration options: [Auto] [800mV] [900mV] PCIE/DMI Slew Rate Allows you set the speed at which the base clock rises or falls. Set a high value for overclocking stability. Configuration options: [Auto] [Slow] [Fast] PCIE/DMI Spread Spectrum Configuration options: [Auto] [Disabled] [Enabled] Cold Boot PCIE Frequency Allows you to set the PCIE Frequency at cold boot. Use the and keys to adjust the value. The values range from 80.000MHz to 200.000MHz with an interval of 0.100MHz. Configuration options: [Auto] [80.0000] - [200.00000] This is only with regards to PCIE clk NOT BCLK. Realtime Memory Timing Allows you to enable or disable realtime memory timing. When set to [Enabled], the system will allow performing realtime memory timing changes after MRC_DONE. Configuration options: [Disabled] [Enabled] SPD Write Disable Allows you to enable or disable setting SPD Write Disable. For security recommendations, SPD write disable bit must be set. Configuration options: [TRUE] [FALSE] PVD Ratio Threshold For the Core Domain PLL, the threshold to switch to lower post divider is 15 by default. You can set a value lower than 15 when pushing high BCLK so that Digitally Controlled Oscillator (DCO) remains at reasonable frequency. Configuration options: [Auto] [1] - [40] 52 ROG Z790 Series (Intel® 14th) BIOS Manual

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52
ROG Z790 Series (Intel
®
14
th
) BIOS Manual
BCLK Slew Rate
Allows you set the speed at which the base clock rises or falls. Set a high value for
overclocking stability.
Configuration options: [Auto] [Slow] [Fast]
BCLK Spread Spectrum
Allows you to reduce the EMI. Disable to get more accurate base clocks.
Configuration options: [Auto] [Disabled] [Enabled]
Initial PCIE Frequency
Allows setting a different PCIE BCLK value during POST. May be useful for setting
a lower PCIE BCLK in scenarios where memory training is not stable at a higher
BCLK (a large frequency gap between BCLK Frequency and Initial frequency is not
recommended). Applies same value as BCLK Frequency if left at default. Use the <+>
and <-> keys to adjust the value. The values range from 80.000MHz to 200.000MHz
with an interval of 0.100MHz.
Configuration options: [Auto] [80.0000] - [200.00000]
PCIE/DMI Amplitude
Allows you to set the signal magnitude of the reference PCIE/DMI CLK supplied to the
processor. Higher values may improve overclocking stability.
Configuration options: [Auto] [800mV] [900mV]
PCIE/DMI Slew Rate
Allows you set the speed at which the base clock rises or falls. Set a high value for
overclocking stability.
Configuration options: [Auto] [Slow] [Fast]
PCIE/DMI Spread Spectrum
Configuration options: [Auto] [Disabled] [Enabled]
Cold Boot PCIE Frequency
Allows you to set the PCIE Frequency at cold boot. Use the <+> and <-> keys to
adjust the value. The values range from 80.000MHz to 200.000MHz with an interval
of 0.100MHz.
Configuration options: [Auto] [80.0000] - [200.00000]
This is only with regards to PCIE clk NOT BCLK.
Realtime Memory Timing
Allows you to enable or disable realtime memory timing. When set to
[Enabled]
, the
system will allow performing realtime memory timing changes after MRC_DONE.
Configuration options: [Disabled] [Enabled]
SPD Write Disable
Allows you to enable or disable setting SPD Write Disable. For security
recommendations, SPD write disable bit must be set.
Configuration options: [TRUE] [FALSE]
PVD Ratio Threshold
For the Core Domain PLL, the threshold to switch to lower post divider is 15 by
default. You can set a value lower than 15 when pushing high BCLK so that Digitally
Controlled Oscillator (DCO) remains at reasonable frequency.
Configuration options: [Auto] [1] - [40]