Biostar IDEQ 220K BIOS MANUAL - Page 21
Ldt & Pci Bus Control
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K8VBK-S7 BIOS Setup 4.3 LDT & PCI BUS CONTROL If you highlight the literal "Press Enter" next to the "LDT & PCI Bus Control" label and then press the enter key, it will take you a submenu with the following options: 4.3.1 Upstream LDT Bus Width The Choices: 8 bit, 16 bit (Default). 4.3.2 Downstream LDT Bus Width The Choices: 8 bit, 16 bit (Default). 4.3.3 LDT Bus Frequency The Choices: 800MHz (Default), Auto, 600MHz, 400MHz, 200MHz. 4.3.4 PCI1 Master 0 WS Write When enabled, writes to the PCI bus are executed with zero-wait states. The Choices: Enabled (default), Disabled. 4.3.5 PCI2 Master 0 WS Write When enabled, writes to the PCI bus are executed with zero-wait states. The Choices: Enabled (default), Disabled. 4.3.6 PCI1 Post Write The Choices: Enabled (default), Disabled. 4.3.7 PCI2 Post Write The Choices: Enabled (default), Disabled. 4.3.8 PCI Delay Transaction The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support compliance with PCI specification. The Choices: Disabled (Default), Enabled. 20
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