EVGA 131-GT-E767-TR User Guide - Page 65

Test Video Memory and display Logos

Page 65 highlights

Award POST Codes Code Name 27 Setup BDA 28 Reserved 29 CPU Speed detect 2A Reserved 2B Init video 2C Reserved 2D Video memory test 2E Reserved 2F Reserved 30 Reserved 31 Reserved 32 Reserved 33 Early keyboard reset 34 Reserved 35 Test DMA Controller 0 36 Reserved 37 Test DMA Controller 1 38 Reserved 39 Test DMA Page Registers 3A Reserved 3B Reserved 3C Test Timer 3D Reserved 3E Test 8259-1 Mask 3F Reserved Description Setup BIOS DATA AREA (BDA) Chipset programming and CPU Speed detect Initialize Video Test Video Memory and display Logos Early Keyboard Reset Test DMA channel 0 Test DMA channel 1 Test DMA Page Registers Test 8254 Timer 0 Counter 2. Verify 8259 Channel 1 masked interrupts by alternately turning off and on the interrupt lines.

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72

Award POST Codes
Code
Name
Description
27
Setup BDA
Setup BIOS DATA AREA (BDA)
28
Reserved
29
CPU Speed
detect
Chipset programming and CPU Speed detect
2A
Reserved
2B
Init video
Initialize Video
2C
Reserved
2D
Video memory
test
Test Video Memory and display Logos
2E
Reserved
2F
Reserved
30
Reserved
31
Reserved
32
Reserved
33
Early keyboard
reset
Early Keyboard Reset
34
Reserved
35
Test DMA
Controller 0
Test DMA channel 0
36
Reserved
37
Test DMA
Controller 1
Test DMA channel 1
38
Reserved
39
Test DMA Page
Registers
Test DMA Page Registers
3A
Reserved
3B
Reserved
3C
Test Timer
Test 8254 Timer 0 Counter 2.
3D
Reserved
3E
Test 8259-1
Mask
Verify 8259 Channel 1 masked interrupts by
alternately turning off and on the interrupt lines.
3F
Reserved