Foxconn Cinema Premium English Manual. - Page 45

► CPU-NB HT Link Control

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3 CPU Configuration CMOS Setup Utility - Copyright (C) 1985-2009, American Megatrends, Inc. CPU Configuration CPU Configuration Help Item Module Version: 13.53 AGESA Version : 3.5.0.0 Allow the CPUs Physical Count : 1 Microcode to be Logical Count : 4 updated/patched AMD Athlon(tm) 9750 Quad-Core Processor Revision : B3 L1 Cache: 512KB L2 Cache: 2048KB L3 Cache: 2MB HT Speed : 1800MHz, Up/Down Width: 16/16bit Speed : 2400MHz, NB Clk: 1800MHz Multipliers unlocked : Yes uCode Patch Level : 0x1000095 CPU Configuration Control Allow Microcode Updates [Enabled] Move Enter:Select +/-/:Value F10:Save ESC:Exit F1:General Help F2/F3:Change colors F9:Optimized Defaults This menu shows most of the CPU specifications. ► Allow Microcode Updates It allows the CPUs Microcode to be updated/patched. ► Secure Virtual Machine This option is used to enable or disable Secure Virtual Machine Mode (SVM) Support. ► Cool 'N' Quiet (Appear only when CPU supports) This option helps lowering down the CPU frequency and voltage when system is idling. When the CPU speed is slowing down, the temperature will drop as well. ► Advanced CPU Settings Press to go to its submenu. ► CPU-NB HT Link Control HT stands for HyperTransport bus. The CPUNB HT Link Control option controls the Link of the CPU to Northbridge HT. ► CPU-NB HT Multiplier HT stands for HyperTransport bus. The CPUNB HT Multiplier option controls the physical speed of the CPU to Northbridge HT link using multipliers ranging 1x to 13x. The physical speed of the link is determined by multiplying the CPU FSB with the CPUNB HT Speed setting. ► HT Uplink Width / HT DownLink Width The coherency refers to the caching of memory, and the HT links between processors are co- herent HT links as the HT protocol includes messages for managing the cache protocol. Other (non processor-processor) HT links are Non-Coherent HT links, as they do not have memory cache. The HyperTransport link width and frequency are initialized between the adjacent coherent and/or noncoherent HyperTransport technology devices during the reset sequence. It is highly recommended to set to [Auto] for overall performance. 38

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3
38
CPU Configuration
This menu shows most of the CPU specifications.
► Allow Microcode Updates
It allows the CPUs Microcode to be updated/patched.
► Secure Virtual Machine
This option is used to enable or disable Secure Virtual Machine Mode (SVM) Support.
► Cool ‘N‘ Quiet (Appear only when CPU supports)
This option helps lowering down the CPU frequency and voltage when system is idling. When
the CPU speed is slowing down, the temperature will drop as well.
► Advanced CPU Settings
Press <Enter> to go to its submenu.
► CPU-NB HT Link Control
HT stands for HyperTransport bus. The CPU<->NB HT Link Control option controls the Link of
the CPU to Northbridge HT.
► CPU-NB HT Multiplier
HT stands for HyperTransport bus. The CPU<->NB HT Multiplier option controls the physical
speed of the CPU to Northbridge HT link using multipliers ranging 1x to 13x. The physical
speed of the link is determined by multiplying the CPU FSB with the CPU<->NB HT Speed
setting.
► HT Uplink Width / HT DownLink Width
The coherency refers to the caching of memory, and the HT links between processors are co-
herent HT links as the HT protocol includes messages for managing the cache protocol. Other
(non processor-processor) HT links are Non-Coherent HT links, as they do not have memory
cache.
The HyperTransport link width and frequency are initialized between the adjacent coherent
and/or noncoherent HyperTransport technology devices during the reset sequence.
It is highly recommended to set to [Auto] for overall performance.
CMOS Setup Utility - Copyright (C) 1985-2009, American Megatrends, Inc.
CPU Configuration
CPU Configuration
Help Item
Module Version: 13.53
AGESA
Version :
3.5.0.0
Allow the CPUs
Physical Count :
1
Microcode to be
Logical Count
:
4
updated/patched
AMD Athlon(tm) 9750 Quad-Core Processor
Revision : B3
L1 Cache:
512KB
L2 Cache:
2048KB
L3 Cache:
2MB
HT Speed
:
1800MHz,
Up/Down Width: 16/16bit
Speed
:
2400MHz,
NB Clk: 1800MHz
Multipliers unlocked
:
Yes
uCode Patch Level
:
0x1000095
CPU Configuration Control
Allow Microcode Updates
↑↓←→:Move
Enter:Select
+/-/:Value
F10:Save
ESC:Exit
F1:General Help
F2/F3:Change colors
F9:Optimized Defaults
[Enabled]