HP Vectra XE310 hp vectra xe310 series 1, technical reference manual - Page 29

Order in Which POST Tests are Performed

Page 29 highlights

BIOS Overview Order in Which POST Tests are Performed Each time the system is powered on, or a reset is performed, the POST is executed. The POST process verifies the basic functionality of the system components and initializes certain system parameters. The POST starts by displaying a graphic screen of the Hewlett-Packard logo when the PC is restarted. Devices, such as memory and newly installed hard disks, are configured automatically. The user is not requested to confirm the change. Newly removed hard disks are detected, and the user is prompted to confirm the new configuration by pressing . Note, though, that the POST does not detect when a hard disk drive has been otherwise changed. During the POST, the BIOS and other ROM data is copied into high-speed shadow RAM. The shadow RAM is addressed at the same physical location as the original ROM in a manner which is completely transparent to applications. It therefore appears to behave as very fast ROM. This technique provides faster access to the system BIOS firmware. The following table lists the POST checkpoint codes written at the start of each test. Checkpoint Code POST Routine Description 02h Verify Real Mode 03h Disable Non-Maskable Interrupt (NMI) 04h Get CPU type 06h Initialize system hardware 08h Initialize chipset with initial POST values 09h Set IN POST flag 0Ah Initialize CPU registers 0Bh Enable CPU cache 0Ch Initialize caches to initial POST values 0Eh Initialize I/O component 0Fh Initialize the local bus IDE 10h Initialize Power Management 11h Load alternate registers with initial POST values 12h Restore CPU control word during warm boot 13h Initialize PCI Bus Mastering devices 14h Initialize keyboard controller 17h Initialize cache before memory autosize 18h 8254 timer initialization 1Ah 8237 DMA controller initialization 1Ch Reset Programmable Interrupt Controller 24h Set ES segment register to 4 GB 26h Enable A20 line 28h Autosize DRAM 29h Initialize POST Memory Manager 2Ah Clear 512 KB base RAM 25

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38

BIOS Overview
25
Order in Which POST Tests are Performed
Each time the system is powered on, or a reset is performed, the POST is executed. The POST process
verifies the basic functionality of the system components and initializes certain system parameters.
The POST starts by displaying a graphic screen of the Hewlett-Packard logo when the PC is restarted.
Devices, such as memory and newly installed hard disks, are configured automatically. The user is not
requested to confirm the change. Newly removed hard disks are detected, and the user is prompted to
confirm the new configuration by pressing
. Note, though, that the POST does not detect when a
hard disk drive has been otherwise changed.
During the POST, the BIOS and other ROM data is copied into high-speed shadow RAM. The shadow
RAM is addressed at the same physical location as the original ROM in a manner which is completely
transparent to applications. It therefore appears to behave as very fast ROM. This technique provides
faster access to the system BIOS firmware.
The following table lists the POST checkpoint codes written at the start of each test.
Checkpoint
Code
POST Routine Description
02h
Verify Real Mode
03h
Disable Non-Maskable Interrupt (NMI)
04h
Get CPU type
06h
Initialize system hardware
08h
Initialize chipset with initial POST values
09h
Set IN POST flag
0Ah
Initialize CPU registers
0Bh
Enable CPU cache
0Ch
Initialize caches to initial POST values
0Eh
Initialize I/O component
0Fh
Initialize the local bus IDE
10h
Initialize Power Management
11h
Load alternate registers with initial POST values
12h
Restore CPU control word during warm boot
13h
Initialize PCI Bus Mastering devices
14h
Initialize keyboard controller
17h
Initialize cache before memory autosize
18h
8254 timer initialization
1Ah
8237 DMA controller initialization
1Ch
Reset Programmable Interrupt Controller
24h
Set ES segment register to 4 GB
26h
Enable A20 line
28h
Autosize DRAM
29h
Initialize POST Memory Manager
2Ah
Clear 512 KB base RAM