HP Vectra XU 6/XXX HP Vectra XU 6/xxx and VT 6/xxx PCs - Technical Reference M - Page 18

Main Memory

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32-bit applications available Yes Yes Yes Yes Yes Yes Partial** No *32-bit operation at the outermost levels, but only 16-bit working internally **With the 32S library The two processors must be operating at the same bus speed and the same processor speed, with the switch settings set accordingly, otherwise erroneous operation will result. MAIN MEMORY The HP Vectra XU/VT 6/xxx PCs use fast page-mode (FPM) DRAM, not extended data-out (EDO) DRAM. The modules are organized in pairs so that a request for a transaction to or from the L2 cache memory will cause two consecutive blocks of 16 bytes (128 bits) to be accessed. Rather than accessing all 128 bits simultaneously, the 64-bit data bus is used more efficiently by interleaving two accesses, the first to one half of the memory bank (for example, A1/B1/C1/D1), the second to the other (for example, A2/B2/C2/D2). Although each memory module stores a line of 64 bits of data (8 bytes), each ECC memory module of the HP Vectra XU 6/xxx PC is, in fact, serviced by a 72-bit Intel proprietary memory bus. The extra bits are generated by the Mem/PL Bridge chip, and are used to implement the error correcting code (ECC). A subsequent error in a memory bit can be corrected, by referring to these extra bits, and hence neither causes the data to be lost, nor corrupted, nor the computation to be aborted (as would have been the case with simple parity detection, as on the HP Vectra XU 5/xx PC). Chip-Set Chips that are involved in Memory Access The Mem/PL Bridge chip (OMC-DP) is an Intel 82452KX. It interfaces between the ProcessorLocal (PL) bus, whose datapath is 64-bits wide, and the Intel proprietary memory bus, whose datapath is 72-bits wide. During a memory-write operation, on the HP Vectra XU 6/xxx PC, the chip generates 8 ECC parity bits. During a memory-read operation, the chip regenerates the 64 data bits from the 72-bit bus, applying error correction when appropriate. Each of the four datapath chips (the Memory Interface Chips, MIC) is an Intel S82451KX, and acts as a two-way switch, able to connect alternately to the A1,B1,C1,D1 side of the interlaced memory, or the A2,B2,C2,D2 side. Since only an 18-bit path can be handled, four units are needed. Datapath units 1, 2, 3 and 4, handle bits 0..17, 18..35, 36..53 and 54..71, respectively. Finally, the memory controller chip (OMC-DC) is an Intel S82453KX. It is responsible for decoding the signals on the address and control paths from the Processor-Local (PL) bus, and for generating the appropriate control signals for the memory banks (such as RAS, CAS, WE# and the address lines). Error Correcting Code Operation The HP Vectra XU 6/xxx PC can tolerate as many as one faulty memory bit per 64-bit line of instruction or data words. The erroneous bit is corrected (automatically and transparently) by the hardware. The computer program continues to execute as if no error had occurred. If two, or more, bits are faulty within any given 64-bit line, the effect is the same as it would have been without error correction. The effect of executing a faulty instruction is always unpredictable, and might cause the program to 'hang'. The effect of reading a faulty data word is often similarly

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32-bit applications
available
Yes
Yes
Yes
Yes
Yes
Yes
Partial**
No
*32-bit operation at the outermost levels, but only 16-bit working internally
**With the 32S library
The two processors must be operating at the same bus speed and the same processor speed, with
the switch settings set accordingly, otherwise erroneous operation will result.
MAIN MEMORY
The
HP Vectra XU/VT 6/xxx PCs
use
fast page-mode
(FPM) DRAM, not
extended data-out
(EDO)
DRAM.
The modules are organized in pairs so that a request for a transaction to or from the L2 cache
memory will cause two consecutive blocks of 16 bytes (128 bits) to be accessed. Rather than
accessing all 128 bits simultaneously, the 64-bit data bus is used more efficiently by
interleaving
two accesses, the first to one half of the memory bank (for example, A1/B1/C1/D1), the second to
the other (for example, A2/B2/C2/D2).
Although each memory module stores a line of 64 bits of data (8 bytes), each ECC memory
module of the
HP Vectra XU 6/xxx PC
is, in fact, serviced by a 72-bit Intel proprietary memory
bus. The extra bits are generated by the Mem/PL Bridge chip, and are used to implement the
error
correcting code
(ECC). A subsequent error in a memory bit can be corrected, by referring to these
extra bits, and hence neither causes the data to be lost, nor corrupted, nor the computation to be
aborted (as would have been the case with simple parity detection, as on the
HP Vectra XU 5/xx
PC
).
Chip-Set Chips that are involved in Memory Access
The Mem/PL Bridge chip (OMC-DP) is an Intel 82452KX. It interfaces between the Processor-
Local (PL) bus, whose datapath is 64-bits wide, and the Intel proprietary memory bus, whose
datapath is 72-bits wide. During a memory-write operation, on the
HP Vectra XU 6/xxx PC
, the
chip generates 8 ECC parity bits. During a memory-read operation, the chip regenerates the 64
data bits from the 72-bit bus, applying error correction when appropriate.
Each of the four datapath chips (the Memory Interface Chips, MIC) is an Intel S82451KX, and acts
as a two-way switch, able to connect alternately to the A1,B1,C1,D1 side of the interlaced
memory, or the A2,B2,C2,D2 side. Since only an 18-bit path can be handled, four units are
needed. Datapath units 1, 2, 3 and 4, handle bits 0..17, 18..35, 36..53 and 54..71, respectively.
Finally, the memory controller chip (OMC-DC) is an Intel S82453KX. It is responsible for decoding
the signals on the address and control paths from the Processor-Local (PL) bus, and for generating
the appropriate control signals for the memory banks (such as RAS, CAS, WE# and the address
lines).
Error Correcting Code Operation
The
HP Vectra XU 6/xxx PC
can tolerate as many as one faulty memory bit per 64-bit line of
instruction or data words. The erroneous bit is corrected (automatically and transparently) by the
hardware. The computer program continues to execute as if no error had occurred.
If two, or more, bits are faulty within any given 64-bit line, the effect is the same as it would have
been without error correction. The effect of executing a faulty instruction is always unpredictable,
and might cause the program to ‘hang’. The effect of reading a faulty data word is often similarly