Hitachi DK23DA-30F Owners Manual - Page 109
Power On and Hardware Reset Timing
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6.4.3 Power On and Hardware Reset Timing Figure 6-18 Power On and Hardware Reset Timing tM RESET- BSY bit tN0 DRDY DRV 0 (device 0) PDIAG(out) DASP(out) DASP(in) tR0 tP0 BSY bit DRDY DRV 1 (device 1) PDIAG- (out) DASP(out) tQ tN1 tR1 tS SYMBOL Description MIN tM RESET- Pulse Width 25 tN0 DRV 0 RESET negation to BSY bit set to one, release PDIAD_ tP0 DRV 0 release DASP-- tR0 DRV 0 sample of DASP- 1 tS DRV 0 sample of PDIAG- 1ms tR1 DRV 1 assert DASP- tN1 DRV 1 negate PDIAG- if asserted tQ DRV 1 assert PDIAG- MAX 400 1 450 31s 400 1 30 Units ms ns ms ms ms ms sec K6602705 Rev.3 08.20.01 - 109 -
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K6602705
Rev.3
08.20.01
- 109 -
6.4.3 Power On and Hardware Reset Timing
Figure 6-18 Power On and Hardware Reset Timing
SYMBOL
Description
MIN
MAX
Units
t
M
RESET- Pulse Width
25
m
s
t
N0
DRV 0 RESET negation to BSY bit set to one,
release PDIAD_
400
ns
t
P0
DRV 0 release DASP--
1
ms
t
R0
DRV 0 sample of DASP-
1
450
ms
t
S
DRV 0 sample of PDIAG-
1ms
31s
-
t
R1
DRV 1 assert DASP-
400
ms
t
N1
DRV 1 negate PDIAG- if asserted
1
ms
t
Q
DRV 1 assert PDIAG-
30
sec
t
M
t
N0
RESET-
BSY bit
DRV 0
t
P0
t
R0
DASP-
DRDY
PDIAG-
t
Q
DRV 1
BSY bit
t
R1
t
S
DASP-
PDIAG-
DRDY
t
N1
DASP-
(out)
(in)
(out)
(out)
(out)
(device 0)
(device 1)