IBM 71413SU Technical Reference - Page 21

XceL4v Dynamic Server Cache, System memory, closer

Page 21 highlights

Applications that run in full 64-bit mode will have access to the full physical memory range, depending on the operating system, and will also have access to the new GPRs as well as to the expanded GPRs. However, it is important to understand that this mode of operation requires not only a 64-bit operating system (and, of course, 64-bit drivers) but also a 64-bit application that has been recompiled to take full advantage of the various enhancements of the 64-bit addressing architecture. For more information about the features of the Xeon quad-core processor, see: http://www.intel.com/products/server/processors/index.htm?iid=process+server For more information about Intel 64, see: http://www.intel.com/technology/architecture-silicon/intel64/index.htm XceL4v Dynamic Server Cache The XceL4v Dynamic Server Cache is a technology developed as part of the IBM XA-64e fourth-generation chipset. It is used in two ways: As a single 4-way server, the XceL4v and its embedded DRAM (eDRAM) is used as a snoop filter to reduce traffic on the front-side bus. It stores a directory of all processor cache lines to minimize snoop traffic on the four front-side buses and minimize cache misses. When the x3950 M2 is configured as a multinode server, this technology dynamically allocates 256 MB of main memory in each node for use as an L4 cache directory and scalability directory. In an 8-way configuration, this means there will be 512 MB of XceL4v cache. Used in conjunction with the XceL4v Dynamic Server Cache is an embedded DRAM (eDRAM), which in single-node configurations contains the snoop filter lookup tables. However, in a multinode configuration, this eDRAM contains the L4 cache directory and the scalability directory. Note: The amount of memory that BIOS reports is minus the portion used for XceL4v cache. System memory The x3850 M2 and x3950 M2 models have either 4 GB or 8 GB of RAM standard, implemented as four or eight 1 GB DIMMs. Memory is PC2-5300 ECC DDR2. Memory is implemented in the x3850 M2 and x3950 M2 using memory cards. The server supports up to four memory cards. Each card has eight DIMM sockets, giving a total of up to 32 DIMM sockets. Some models have two memory cards and some have all four cards standard. Table 3 on page 12 provides more detail about this topic. Using 8 GB DIMMs in every socket, the server can hold 256 GB of RAM. With four nodes, the combined complex can hold up to 1 TB of RAM. With a multinode configuration, the memory in all nodes is combined to form a single, coherent physical address space. The resulting system has the property such that for any given region of physical memory, some processors are closer to it than other processors. IBM System x3950 M2 and x3850 M2 Technical Introduction 21

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IBM System x3950 M2 and x3850 M2 Technical Introduction
21
Applications that run in full 64-bit mode will have access to the full physical memory
range, depending on the operating system, and will also have access to the new GPRs
as well as to the expanded GPRs. However, it is important to understand that this
mode of operation requires not only a 64-bit operating system (and, of course, 64-bit
drivers) but also a 64-bit application that has been recompiled to take full advantage of
the various enhancements of the 64-bit addressing architecture.
For more information about the features of the Xeon quad-core processor, see:
For more information about Intel 64, see:
XceL4v Dynamic Server Cache
The XceL4v Dynamic Server Cache is a technology developed as part of the IBM XA-64e
fourth-generation chipset. It is used in two ways:
±
As a single 4-way server, the XceL4v and its embedded DRAM (eDRAM) is used as a
snoop filter to reduce traffic on the front-side bus. It stores a directory of all processor
cache lines to minimize snoop traffic on the four front-side buses and minimize cache
misses.
±
When the x3950 M2 is configured as a multinode server, this technology dynamically
allocates 256 MB of main memory in each node for use as an L4 cache directory and
scalability directory. In an 8-way configuration, this means there will be 512 MB of XceL4v
cache.
Used in conjunction with the XceL4v Dynamic Server Cache is an embedded DRAM
(eDRAM), which in single-node configurations contains the snoop filter lookup tables.
However, in a multinode configuration, this eDRAM contains the L4 cache directory and the
scalability directory.
System memory
The x3850 M2 and x3950 M2 models have either 4 GB or 8 GB of RAM standard,
implemented as four or eight 1 GB DIMMs. Memory is PC2-5300 ECC DDR2.
Memory is implemented in the x3850 M2 and x3950 M2 using memory cards. The server
supports up to four memory cards. Each card has eight DIMM sockets, giving a total of up to
32 DIMM sockets. Some models have two memory cards and some have all four cards
standard. Table 3 on page 12 provides more detail about this topic.
Using 8 GB DIMMs in every socket, the server can hold 256 GB of RAM. With four nodes, the
combined complex can hold up to 1 TB of RAM.
With a multinode configuration, the memory in all nodes is combined to form a single,
coherent physical address space. The resulting system has the property such that for any
given region of physical memory, some processors are
closer
to it than other processors.
Note:
The amount of memory that BIOS reports is minus the portion used for XceL4v
cache.