Intel BOXD845BGSE Product Specification - Page 52

PCI Interrupt Routing Map

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Intel Desktop Board D845BG/D845PT Technical Product Specification 2.7 PCI Interrupt Routing Map This section describes interrupt sharing and how the interrupt signals are connected between the PCI bus connectors and onboard PCI devices. The PCI specification specifies how interrupts can be shared between devices attached to the PCI bus. In most cases, the small amount of latency added by interrupt sharing does not affect the operation or throughput of the devices. In some special cases where maximum performance is needed from a device, a PCI device should not share an interrupt with other PCI devices. Use the following information to avoid sharing an interrupt with a PCI add-in card. PCI devices are categorized as follows to specify their interrupt grouping: • INTA: By default, all add-in cards that require only one interrupt are in this category. For almost all cards that require more than one interrupt, the first interrupt on the card is also classified as INTA. • INTB: Generally, the second interrupt on add-in cards that require two or more interrupts is classified as INTB. (This is not an absolute requirement.) • INTC and INTD: Generally, a third interrupt on add-in cards is classified as INTC and a fourth interrupt is classified as INTD. The ICH2 has eight programmable interrupt request (PIRQ) input signals. All PCI interrupt sources either onboard or from a PCI add-in card connect to one of these PIRQ signals. Some PCI interrupt sources are electrically tied together on the D845BG and D845PT boards and therefore share the same interrupt. Table 17 shows an example of how the PIRQ signals are routed on the D845BG and D845PT boards. For example, using Table 17 as a reference, assume an add-in card using INTB is plugged into PCI bus connector 3. In PCI bus connector 3, INTB is connected to PIRQB, which is already connected to the SMBus. The add-in card in PCI bus connector 3 now shares interrupts with these onboard interrupt sources. 52

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Intel Desktop Board D845BG/D845PT Technical Product Specification
52
2.7 PCI Interrupt Routing Map
This section describes interrupt sharing and how the interrupt signals are connected between the
PCI bus connectors and onboard PCI devices.
The PCI specification specifies how interrupts can
be shared between devices attached to the PCI bus.
In most cases, the small amount of latency
added by interrupt sharing does not affect the operation or throughput of the devices.
In some
special cases where maximum performance is needed from a device, a PCI device should not share
an interrupt with other PCI devices.
Use the following information to avoid sharing an interrupt
with a PCI add-in card.
PCI devices are categorized as follows to specify their interrupt grouping:
•
INTA:
By default, all add-in cards that require only one interrupt are in this category.
For
almost all cards that require more than one interrupt, the first interrupt on the card is also
classified as INTA.
•
INTB:
Generally, the second interrupt on add-in cards that require two or more interrupts is
classified as INTB.
(This is not an absolute requirement.)
•
INTC and INTD:
Generally, a third interrupt on add-in cards is classified as INTC and a
fourth interrupt is classified as INTD.
The ICH2 has eight programmable interrupt request (PIRQ) input signals.
All PCI interrupt
sources either onboard or from a PCI add-in card connect to one of these PIRQ signals.
Some PCI
interrupt sources are electrically tied together on the D845BG and D845PT boards and therefore
share the same interrupt.
Table 17 shows an example of how the PIRQ signals are routed on the
D845BG and D845PT boards.
For example, using Table 17 as a reference, assume an add-in card using INTB is plugged into PCI
bus connector 3.
In PCI bus connector 3, INTB is connected to PIRQB, which is already
connected to the SMBus.
The add-in card in PCI bus connector 3 now shares interrupts with these
onboard interrupt sources.