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Revision History Intel® Server Boards S3200SH/S3210SH TPS Revision History Date Sept. 2007 Oct. 2007 Jan. 2008 Apr. 2008 July 2008 Sept. 2008 Jan. 2009 Feb. 2009 May 2010 Revision Number 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Initial release. Modifications Added new updates. Corrected some document errors. Added Intel® Embedded Server RAID Technology. Added CMOS Clear instructions Updated Diagnostic LEDs graphic Grammatical corrections. Grammatical corrections and minor updates. Removed CCC. Disclaimers Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. This document contains information on products in the design phase of development. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local sales office that you have the latest datasheet before finalizing a design. The Intel Server boards Snow Hill family may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. This document and the software described in it is furnished under license and may only be used or copied in accordance with the terms of the license. The information in this manual is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document. Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. Intel, Pentium, Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation. *Other brands and names may be claimed as the property of others. Copyright © Intel Corporation 2007-2010. ii Revision 1.8 Intel Order Number: E14960-009

Section	Page
1. Introduction	13
1.1 Chapter Outline	13
1.2 Server Board Use Disclaimer	13
2. Server Board Overview	14
2.1 Server Board Feature Set	14
2.2 Server Board Layout	22
2.2.1 Server Board Mechanical Drawings	23
3. Functional Architecture	25
3.1 Processor Sub-System	27
3.1.1 Processor Voltage Regulator Down (VRD)	27
3.1.2 Reset Configuration Logic	27
3.2 Intel® 3200/3210 Chipset	28
3.2.1 Intel® 3200/3210 Chipset MCH: Memory Control Hub	28
3.2.1.1 Segment F PCI Express* x8	29
3.2.1.2 MCH Memory Sub-System Overview	30
3.2.1.4 Memory Population Rules and Configurations	30
3.2.2 PCI-X Hub (LX board SKU only)	31
3.2.2.1 Segment E 64bit/133MHz PCI-X Subsystem	31
3.2.2.1.1 Device IDs (IDSEL)	31
3.2.2.1.2 Segment E Arbitration	31
3.2.3 Intel® ICH9R: I/O Controller Hub 9R	32
3.2.3.1 Direct Media Interface (DMI)	32
3.2.3.2 Controller Link (M-Link)	32
3.2.3.3 PCI Express* Interfaces	32
3.2.3.4 Serial ATA II Interface	32
3.2.3.5 PCI Interface	32
3.2.3.6 Low Pin Count Interface (LPC)	32
3.2.3.7 Compatibility Modules	33
3.2.3.8 Universal Serial Bus (USB) Controller	33
3.2.3.9 Real Time Clock (RTC)	33
3.2.3.10 GPIO	33
3.2.3.11 Enhanced Power Management	33
3.2.3.12 System Management Interface	34
3.2.3.13 Intel® Quiet System Technology (Intel® QST)	34
3.2.3.14 Serial Peripheral Interface (SPI)	34
3.2.3.15 Manageability	36
3.2.3.16 Unused Intel® ICH9 Interfaces on the Server Board	36
3.2.3.17 PCI Express* x4 Sub-system	37
3.2.3.18 PCI	37
3.2.3.19 SATA Controller	37
3.2.3.20 Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)	37
3.2.3.21 Advanced Programmable Interrupt Controller (APIC)	37
3.2.3.22 Universal Serial Bus (USB) Controller	37
3.2.3.23 Enhanced Power Management	37
3.3 Memory Sub-System	38
3.3.1 Memory Configuration	38
3.3.2 Memory DIMM Support	40
3.4 I/O Sub-System	40
3.4.1 PCI Subsystem	40
3.4.1.1 P32-A: 32-bit, 33-MHz PCI Sub-system	41
3.4.1.1.1 Device IDs (IDSEL)	41
3.4.1.1.2 Segment A Arbitration	41
3.4.1.2 PCI Interface for Video subsystem	42
3.4.2 Interrupt Routing	42
3.4.2.1 Legacy Interrupt Routing	42
3.4.2.2 APIC Interrupt Routing	43
3.4.2.3 Legacy Interrupt Sources	43
3.4.2.4 Serialized IRQ Support	43
3.4.3 PCI Error Handling	44
3.5 BMC Controller	48
3.6 PCI Express* to PCI-X Bridge 6702PXH (PXH-V) (LX Board SKU Only)	50
3.7 Clock Generator	50
3.8 Super I/O	50
3.9 GigE Controller 82541PI	51
3.10 GigE PHY	51
3.11 On-Board Components	51
3.11.1 Video Support	51
3.11.1.1 Video Modes	53
3.12 Replacing the Back-Up Battery	54
4. System BIOS	55
4.1 BIOS Identification String	55
4.2 Logo / Diagnostic Window	56
4.3 BIOS Setup Utility	56
4.3.1 Operation	56
4.3.1.1 Setup Page Layout	56
4.3.1.2 Entering BIOS Setup	57
4.3.1.3 Keyboard Commands	57
4.3.1.4 Menu Selection Bar	58
4.3.2 Server Platform Setup Screens	59
4.3.2.1 Main Screen	59
4.3.2.2 Advanced Screen	62
4.3.2.2.1 Processor Screen	63
4.3.2.2.2 Memory Screen	64
4.3.2.2.3 SATA Controller Screen	66
4.3.2.2.4 Serial Ports Screen	68
4.3.2.2.5 USB Configuration Screen	69
4.3.2.2.6 PCI Screen	71
4.3.2.3 Security Screen	72
4.3.2.4 Server Management Screen	74
4.3.2.4.1 Console Redirection Screen	75
4.3.2.5 Server Management System Information Screen	77
4.3.2.6 Boot Options Screen	78
4.3.2.6.1 Hard Disk Order Screen	79
4.3.2.6.2 CDROM Order Screen	81
4.3.2.6.3 Floppy Order Screen	81
4.3.2.6.4 Network Device Order Screen	82
4.3.2.6.5 BEV Device Order Screen	83
4.3.2.7 Boot Manager Screen	84
4.3.2.8 Error Manager Screen	84
4.3.2.9 Exit Screen	85
4.3.2.9.1 Fan Speed Control Methodology	86
4.4 Loading BIOS Defaults	87
4.5 Multiple Boot Blocks	87
4.6 Recovery Mode	87
4.7 Intel® Matrix Storage Manager	88
4.8 Intel® Embedded Server RAID Technology II Support	88
5. Error Reporting and Handling	89
5.1 Error Handling and Logging	89
5.1.1 Error Sources and Types	89
5.1.2 Error Logging via SMI Handler	90
5.1.2.1 PCI Bus Error	90
5.1.2.2 PCI Express* Errors	90
5.1.2.3 Memory Errors	90
5.1.3 SMBIOS Type 15	90
5.1.4 Logging Format Conventions	90
5.2 Error Messages and Error Codes	92
5.2.1 Diagnostic LEDs	92
5.2.2 POST Code Checkpoints	93
5.2.3 POST Error Messages and Handling	96
5.2.4 POST Error Beep Codes	97
5.2.5 POST Error Pause Option	97
6. Connectors and Jumper Blocks	98
6.1 Power Connectors	98
6.1.1 Main Power Connector	98
6.2 Intel® Riser Card for L SKU	99
6.3 SMBus Connector	99
6.4 Front Panel Connector	99
6.5 I/O Connectors	100
6.5.1 VGA Connector	100
6.5.2 NIC Connectors	100
6.5.3 SATA Connectors	101
6.5.4 Floppy Controller Connector	101
6.5.5 Serial Port Connectors	102
6.5.6 Keyboard and Mouse Connector	103
6.5.7 USB Connector	103
6.6 Fan Headers	104
6.7 Miscellaneous Headers and Connectors	104
6.7.1 Back Panel I/O Connectors	104
6.7.2 Chassis Intrusion Header	105
6.7.3 HDD Active LED Header	105
6.7.4 IPMB	105
6.7.5 HSBP	105
6.7.6 SATA SGPIO	106
6.8 Jumper Blocks	106
6.8.1 CMOS Clear and Password Reset Usage Procedure	106
6.8.2 BMC Force Update Procedure	107
7. Absolute Maximum Ratings	108
7.1 Mean Time Between Failures (MTBF) Test Results	108
7.2 Calculated Mean Time Between Failures (MTBF)	108
8. Design and Environmental Specifications	109
8.1 Power Budget	109
8.2 Power Supply Specifications	110
8.2.1 Power Timing Requirements	110
8.2.2 Dynamic Loading	113
8.2.3 AC Line Transient Specification	113
8.2.4 AC Line Fast Transient (EFT) Specification	114
8.3 Product Regulatory Compliance	114
8.3.1 Product Safety Compliance	114
8.3.2 Product EMC Compliance – Class A Compliance	115
8.3.3 Certifications / Registrations / Declarations	115
8.3.4 Product Regulatory Compliance Markings	117
8.4 Electromagnetic Compatibility Notices	118
8.4.1 FCC (USA)	118
8.4.2 ICES-003 (Canada)	119
8.4.3 Europe (CE Declaration of Conformity)	119
8.4.4 VCCI (Japan)	119
8.4.5 Taiwan Declaration of Conformity (BSMI)	119
8.4.6 Korean Compliance (RRL)	120
8.5 Mechanical Specifications	121
9. Hardware Monitoring	124
9.1 Chassis Intrusion	124

Match case Limit results 1 per page

Revision History

Intel® Server Boards S3200SH/S3210SH TPS

Revision 1.8

Intel Order Number: E14960-009

Revision History

Date

Revision Number

Modifications

Sept. 2007

1.0

Initial release.

Oct. 2007

1.1

Added new updates.

Jan. 2008

1.2

Corrected some document errors.

Apr. 2008

1.3

Added Intel

Embedded Server RAID Technology.

July 2008

1.4

Added CMOS Clear instructions

Sept. 2008

1.5

Updated Diagnostic LEDs graphic

Jan. 2009

1.6

Grammatical corrections.

Feb. 2009

1.7

Grammatical corrections and minor updates.

May 2010

1.8

Removed CCC.

Disclaimers

Information in this document is provided in connection with Intel

products. No license, express or implied, by

estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's

Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any

express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property

right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make

changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or

"undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or

incompatibilities arising from future changes to them.

This document contains information on products in the design phase of development. Do not finalize a design with

this information. Revised information will be published when the product is available. Verify with your local sales office

that you have the latest datasheet before finalizing a design.

The Intel Server boards Snow Hill family may contain design defects or errors known as errata which may cause the

product to deviate from published specifications. Current characterized errata are available on request.

This document and the software described in it is furnished under license and may only be used or copied in

accordance with the terms of the license. The information in this manual is furnished for informational use only, is

subject to change without notice, and should not be construed as a commitment by Intel Corporation. Intel

Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or

any software that may be provided in association with this document.

Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or

transmitted in any form or by any means without the express written consent of Intel Corporation.

Intel, Pentium, Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation.

*Other brands and names may be claimed as the property of others.