Intel S3200SH Product Specification - Page 49
Integrated BMC Block Diagram - fan speed
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Intel® Server Boards S3200SH/S3210SH TPS Functional Architecture Eight Fan Tach Inputs Four Pulse Width Modulators (PWM) Chassis Intrusion Logic with battery backed general purpose register LED support with programmable blink rate control Programmable IO Port snooping, which can be used to snoop on Port 80h Unique Chip ID for each part, burned at the time of production testing Hardware 32-bit Random Number generator JTAG Master interface On-Chip Test Infrastructure for testing BMC firmware Graphics Controller Subsystem Integrated Matrix Graphics Core 2D Hardware Graphics Acceleration DDR2 memory interface supports up to 128 Mbytes of memory Supports all display resolutions up to 1600 x 1200 16 bpp @ 75 Hz High speed Integrated 24-bit RAMDAC Single lane PCI Express* host interface Integrated BMC Block Diagram USB to Host Code Memory LPC Interface To Host ARM926EJ-S 16K D & I Cache Interrupt Controller RTC & General Purpose TImers (3) Fan Tach (12) PWM (4) UART I2C (3) (6) BMC & KVMS Subsystem ADC Thermal USB 1.1 & USB 2.0 Ethernet MAC with RMII (2) Crypto Accelerator LPC Master, JTAG Master, & SPI FLash DDR-II 16-bit Memory Controller UART (3) GPIO KCS BT & Mailboxes System Wakeup Control LPC Interface LPC to SPI Flash Bridge Watchdog Timer BMC & KVMS Subsystem Real Time Clock Interface (external RTC) Graphics Controller Graphics Subsystem JTAG Master DDR-II (up to 667MHz) Video Output PCIe x1 Interface Revision 1.8 37 Intel Order Number: E14960-009