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POST Error Beep Codes

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Intel® Workstation Board S5000XVN TPS Appendix D: POST Code Errors POST Error Beep Codes The following table lists POST error beep codes. Prior to system Video initialization, the BIOS uses these beep codes to inform users on error conditions. The beep code is followed by a user-visible code on POST Progress LEDs. Table 49. POST Error Beep Codes Beeps Error Message POST Progress Code Description 3 Memory error 6 BIOS rolling back error System halted because a fatal error related to the memory was detected. The system has detected a corrupted BIOS in the flash part and is rolling back to the last good BIOS. The BMC may generate beep codes upon detection of failure conditions. Beep codes are sounded each time the problem is discovered, such as on each power-up attempt, but are not sounded continuously. The following table lists codes common across all Intel® server boards and systems that use the Intel® 5000 chipset. Each digit in the code is represented by a sequence of beeps whose count is equal to the digit. Table 50. BMC Beep Codes Code Reason for Beep Associated Sensors 1-5-2-1 1-5-2-2 1-5-2-3 1-5-2-4 1-5-4-2 1-5-4-3 1-5-4-4 CPU: Empty slot/population error - Processor slot 1 is not populated. CPU: No processors (terminators only) CPU: Configuration error (e.g., VID mismatch) CPU: Configuration error (e.g, BSEL mismatch) Power fault: DC power unexpectedly lost (power good dropout) Chipset control failure Power control fault CPU Population Error N/A N/A N/A Power Unit - power unit failure offset N/A Power Unit - soft power control failure offset Supported? Yes No No No Yes No Yes Revision 1.5 93 Intel order number: D66403-006

Section	Page
1. Introduction	10
1.1 Chapter Outline	10
1.2 Server Board Use Disclaimer	10
2. Overview	11
2.1 Workstation Board Feature Set	11
2.2 Workstation Board Layout	12
2.2.1 Workstation Board Connector and Component Layout	13
2.2.2 Workstation Board Mechanical Drawings	15
2.2.3 Workstation Board ATX I/O Layout	21
3. Functional Architecture	22
3.1 Intel® 5000X Memory Controller Hub (MCH)	23
3.1.1 System Bus Interface	23
3.1.2 Processor Support	23
3.1.2.1 Processor Population Rules	24
3.1.2.2 Common Enabling Kit (CEK) Design Support	24
3.1.3 Memory Subsystem	25
3.1.3.1 Memory RASUM Features	27
3.1.3.2 Supported Memory	27
3.1.3.3 DIMM Population Rules and Supported DIMM Configurations	28
3.1.3.3.1 Minimum Non-Mirrored Mode Configuration	30
3.1.3.4 Non-mirrored Mode Memory Upgrades	30
3.1.3.4.1 Mirrored Mode Memory Configuration	31
3.1.3.4.2 Sparing Mode Memory Configuration	31
3.1.3.4.2.1 Single Branch Mode Sparing	32
3.1.3.4.2.2 Dual Branch Mode Sparing	32
3.1.4 Snoop Filter	33
3.2 Enterprise South Bridge (ESB2-E)	33
3.2.1 PCI Subsystem	33
3.2.1.1 PCI32: 32-bit, 33-MHz PCI Subsystem	34
3.2.1.2 PXA: 64-bit, 133-MHz PCI Subsystem	34
3.2.1.3 PE0: One x4 PCI Express* Bus Segment	34
3.2.1.4 PE1: One x4 PCI Express* Bus Segment	34
3.2.1.5 PE2: One x4 PCI Express* Bus Segment	35
3.2.1.6 PE4, PE5, PE6, PE7: Four x4 PCI Express* Bus Segments	35
3.2.1.7 PCI Express* Riser Slot	35
3.2.2 Serial ATA Support	35
3.2.2.1 Intel® Embedded Server RAID Technology II Support	35
3.2.2.2 Intel® Embedded Server RAID Technology Option ROM	36
3.2.3 Parallel ATA (PATA) Support	36
3.2.4 USB 2.0 Support	36
3.3 Audio Codec	37
3.4 SAS Controller	38
3.4.1 SAS RAID Support	38
3.4.2 SAS/SATA Connector Sharing	38
3.5 Network Interface Controller (NIC)	38
3.5.1 Intel® I/O Acceleration Technolgy (Intel® I/OAT)	39
3.5.2 MAC Address Definition	39
3.6 Super I/O	40
3.6.1 Serial Ports	40
3.6.2 Floppy Disk Controller	40
3.6.3 Keyboard and Mouse Support	40
3.6.4 Wake-up Control	40
3.6.5 System Health Support	41
3.6.6 Trusted Platform Module (TPM)	41
4. Platform Management	42
5. Connector/Header Locations and Pin-outs	44
5.1 Board Connector Information	44
5.2 Power Connectors	45
5.3 System Management Headers	46
5.3.1 LCP/AUX IPMB Header	46
5.3.2 IPMB Header	47
5.3.3 HSBP Header	47
5.3.4 SGPIO Header	47
5.3.5 SES I2C	47
5.3.6 HDD Activity LED Header	47
5.4 Front Panel Connector	48
5.5 I/O Connectors	48
5.5.1 NIC Connectors	48
5.5.2 IDE Connector	49
5.5.3 SATA/SAS Connectors	50
5.5.4 Serial Port Connectors	50
5.5.5 Keyboard and Mouse Connector	51
5.5.6 USB Connector	51
5.5.7 CD-IN Header	52
5.5.8 Audio Connectors	52
5.6 Fan Headers	53
6. Jumper Blocks	55
6.1 CMOS Clear and Password Reset Usage Procedure	56
6.2 BMC Force Update Procedure	56
6.3 BIOS Select Jumper	57
7. Intel® Light Guided Diagnostics	58
7.1 5 Volt Standby LED	58
7.2 Fan Fault LEDs	59
7.3 System ID LED and System Status LED	60
7.3.1 System Status LED – BMC Initialization	62
7.4 DIMM Fault LEDs	62
7.5 Processor Fault LEDs	63
7.6 Post Code Diagnostic LEDs	63
8. Design and Environmental Specifications	65
8.1 Intel® Workstation Board S5000XVN Design Specifications	65
8.2 Board-level MTBF	66
8.3 Workstation Board Power Requirements	66
8.3.1 Processor Power Support	68
8.4.1 Grounding	69
8.4.2 Standby Outputs	69
8.4.3 Remote Sense	69
8.4.4 Voltage Regulation	69
8.4.5 Dynamic Loading	70
8.4.6 Capacitive Loading	70
8.4.7 Ripple/Noise	71
8.4.8 Timing Requirements	72
8.4.9 Residual Voltage Immunity in Standby Mode	74
9. Regulatory and Certification Information	75
9.1 Product Regulatory Compliance	75
9.1.1 Product Safety Compliance	75
9.1.2 Product EMC Compliance – Class A Compliance	75
9.1.3 Certifications/Registrations/Declarations	76
9.2 Product Regulatory Compliance Markings	76
9.3 Electromagnetic Compatibility Notices	77
9.3.1 FCC Verification Statement (USA)	77
9.3.2 ICES-003 (Canada)	77
9.3.3 Europe (CE Declaration of Conformity)	78
9.3.4 VCCI (Japan)	78
9.3.5 BSMI (Taiwan)	78
9.3.6 RRL (Korea)	78
9.4 Restriction of Hazardous Substances (RoHS) Compliance	79
Appendix A: Integration and Usage Tips	80
Appendix B: BMC Sensor Tables	81
Appendix C: POST Code Diagnostic LED Decoder	96
Appendix D: POST Code Errors	99
Appendix E: Supported Intel® Server Chassis	103
Glossary	104