Intel S5000XVNSATAR Product Specification - Page 29
Table 7. DIMM Population Rules
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Functional Architecture Intel® Workstation Board S5000XVN TPS In the following table, the following codes are used: VP: Validated configuration and the slot is populated SP: Supported, but not validated configuration, and the slot is populated NP: Slot is not populated Table 7. DIMM Population Rules Branch 0 Channel A Channel B DIMM_A1 DIMM_A2 DIMM_B1 DIMM B2 VP NP NP NP VP NP VP NP SP SP SP SP VP NP VP NP SP SP SP SP VP VP VP VP Branch 1 Channel C Channel D DIMM C1 DIMM C2 DIMM D1 DIMM D2 NP NP NP NP NP NP NP NP NP NP NP NP VP NP VP NP SP NP SP NP VP VP VP VP Mirroring Possible No No No VP, Yes No VP, Yes Sparing Possible No No SP, Yes, Branch 0 only No SP, Yes, Branch 0 only VP, Yes, Branch 0 and Branch 1 Notes: Single channel mode is only tested and supported with a 512 MB x8 FBDIMM installed in DIMM Socket A1. The supported memory configurations must meet population rules defined above. For best performance, you should install a minimum of four DIMMs across memory branches. Although mixed DIMM capacities between channels are supported, Intel® does not validate FBDIMMs in mixed DIMM configurations. 20 Revision 1.5 Intel order number: D66403-006