Intel S5520HCT Product Specification - Page 48

Memory Population and Upgrade Rules

Page 48 highlights

Functional Architecture Intel® Server Boards S5520HC, S5500HCV, and S5520HCT TPS 3.3.8.2 Independent Channel Mode In the Independent Channel mode, you can populate multiple channels on any channel in any order. The Independent Channel mode provides less RAS capability but better DIMM isolation in case of errors. Moreover, it allows the best interleave mode possible and thereby increases performance and thermal characteristics. Adjacent slots on a DDR3 Channel from the Intel® Xeon® Processor 5500 series do not need matching size and organization in independent channel mode. However, the speed of the channel is configured to the maximum common speed of the DIMMs. The Single Channel mode is established using the Independent Channel mode by populating the DIMM slots from Channel A. 3.3.8.3 Mirrored Channel Mode The Mirrored Channel mode is a RAS feature in which two identical images of memory channel data are maintained, providing maximum redundancy. On the Intel® Xeon® Processor 5500 series based Intel® server boards, the mirroring is achieved across channels. Active channels hold the primary image and the other channels hold the secondary image of the system memory. The integrated memory controller in the Intel® Xeon® Processor 5500 series alternates between both channels for read transactions. Write transactions are issued to both channels under normal circumstances. The mirrored image is a redundant copy of the primary image; therefore, the system can continue to operate despite the presence of sporadic uncorrectable errors, resulting in 100% data recovery. In Mirrored Channel mode, channel A (or D) and channel B (or E) function as the mirrors, while Channel C (or F) is unused. The effective system memory is reduced by at least one-half. For example, if the system is operating in the Mirrored Channel mode and the total size of the DDR3 DIMMs is 2 GB, then the effective memory size is 1 GB because half of the DDR3 DIMMs are the secondary images. If Channel C (or F) is populated, the BIOS will disable the Mirrored Channel mode. This is because the BIOS always gives preference to the maximization of memory capacity over memory RAS because RAS is an enhanced feature. The BIOS provides a setup option to enable mirroring if the current DIMM population is valid for the Mirrored Channel mode of operation. When memory mirroring is enabled, the BIOS attempts to configure the memory system accordingly. If the BIOS finds the DIMM population is not suitable for mirroring, it falls back to the default Independent Channel mode with maximum interleaved memory. 3.3.9 Memory Population and Upgrade Rules Populating and upgrading the system memory requires careful positioning of the DDR3 DIMMs based on the following factors: • Current RAS mode of operation • Existing DDR3 DIMM population • DDR3 DIMM characteristics 34 Revision 1.8 Intel order number E39529-013

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Functional Architecture
Intel® Server Boards S5520HC, S5500HCV, and S5520HCT TPS
Revision 1.8
Intel order number E39529-013
34
3.3.8.2
Independent Channel Mode
In the Independent Channel mode, you can populate multiple channels on any channel in any
order. The Independent Channel mode provides less RAS capability but better DIMM isolation
in case of errors. Moreover, it allows the best interleave mode possible and thereby increases
performance and thermal characteristics.
Adjacent slots on a DDR3 Channel from the Intel
®
Xeon
®
Processor 5500 series do not need
matching size and organization in independent channel mode. However, the speed of the
channel is configured to the maximum common speed of the DIMMs.
The Single Channel mode is established using the Independent Channel mode by populating
the DIMM slots from Channel A.
3.3.8.3
Mirrored Channel Mode
The Mirrored Channel mode is a RAS feature in which two identical images of memory channel
data are maintained, providing maximum redundancy. On the Intel
®
Xeon
®
Processor 5500
series based Intel
®
server boards, the mirroring is achieved across channels. Active channels
hold the primary image and the other channels hold the secondary image of the system memory.
The integrated memory controller in the Intel
®
Xeon
®
Processor 5500 series alternates between
both channels for read transactions. Write transactions are issued to both channels under
normal circumstances. The mirrored image is a redundant copy of the primary image; therefore,
the system can continue to operate despite the presence of sporadic uncorrectable errors,
resulting in 100% data recovery.
In Mirrored Channel mode, channel A (or D) and channel B (or E) function as the mirrors, while
Channel C (or F) is unused. The effective system memory is reduced by at least one-half. For
example, if the system is operating in the Mirrored Channel mode and the total size of the DDR3
DIMMs is 2 GB, then the effective memory size is 1 GB because half of the DDR3 DIMMs are
the secondary images.
If Channel C (or F) is populated, the BIOS will disable the Mirrored Channel mode. This is
because the BIOS always gives preference to the maximization of memory capacity over
memory RAS because RAS is an enhanced feature.
The BIOS provides a setup option to enable mirroring if the current DIMM population is valid for
the Mirrored Channel mode of operation. When memory mirroring is enabled, the BIOS
attempts to configure the memory system accordingly. If the BIOS finds the DIMM population is
not suitable for mirroring, it falls back to the default Independent Channel mode with maximum
interleaved memory.
3.3.9
Memory Population and Upgrade Rules
Populating and upgrading the system memory requires careful positioning of the DDR3 DIMMs
based on the following factors:
Current RAS mode of operation
Existing DDR3 DIMM population
DDR3 DIMM characteristics