Intel SC5650 Technical Product Specification - Page 77

Table 67. SMBAlert# Signal Characteristics

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Intel® Server Chassis SC5650 TPS Power Sub-system The SMBAlert# signal will automatically be cleared when the cause of the event is no longer present. Table 67. SMBAlert# Signal Characteristics Signal Type (Active Low) Alert# = High Alert# = Low Logic level low voltage, Isink=4 mA Logic level high voltage, Isink=50 μA Sink current, Alert# = low Sink current, Alert# = high Alert# rise and fall time Open collector / drain output from power supply. Pullup to VSB located in system. OK Power Alert to system MIN MAX 0 V 0.4 V 5.25 V 4 mA 50 μA 100 μs 2.3.5 PMBus The PMBus features included in this specification are requirements for ac/dc silver box power supply for use in mainstream server systems. This specification is based on the PMBus specifications parts I and II, revision 1.2. 2.3.5.1 Related Documents PMBus™ Power System Management Protocol Specification Part I - General Requirements, Transport And Electrical Interface; Revision 1.2 PMBus™ Power System Management Protocol Specification Part II - Command Language; Revision 1.2 System Management Bus (SMBus) Specification Version 2.0 2.3.5.2 Addressing The power supply PMBus device address locations are shown below. For redundant systems there are up to three signals to set the address location of the power supply once it is installed in the system; Address2, Address1, Address0. For non-redundant systems the power supply device address location should be B0h. System addressing Address2/Address1/ Address0 0/0/0 0/0/1 0/1/0 0/1/1 1/0/0 1/0/1 1/1/0 1/1/1 PMBus device read addresses 2 B0h/B1h1 B2h/B3h B4h/B5h B6h/B7h B8h/B9h BAh/BBh BCh/BDh BEh/BFh 1 Non-redundant power supplies will use the 0/0/0 address location 2 The addressing method uses the 7 MSB bits to set the address and the LSB to define whether a device is reading or writing. The addresses defined above use 8 bits including the read/write bit. IPMI FRU Addressing Revision 1.2 63 Intel order number E39531-004

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Intel® Server Chassis SC5650 TPS
Power Sub-system
Revision 1.2
Intel order number E39531-004
63
The SMBAlert# signal will automatically be cleared when the cause of the event is no longer
present.
Table 67. SMBAlert# Signal Characteristics
Signal Type (Active Low)
Open collector / drain output from power supply. Pull-
up to VSB located in system.
Alert# = High
OK
Alert# = Low
Power Alert to system
MIN
MAX
Logic level low voltage, Isink=4 mA
0 V
0.4 V
Logic level high voltage, Isink=50
μ
A
5.25 V
Sink current, Alert# = low
4 mA
Sink current, Alert# = high
50
μ
A
Alert# rise and fall time
100
μ
s
2.3.5
PMBus
The PMBus features included in this specification are requirements for ac/dc silver box power
supply for use in mainstream server systems. This specification is based on the PMBus
specifications parts I and II, revision 1.2.
2.3.5.1
Related Documents
PMBus™ Power System Management Protocol Specification Part I – General Requirements,
Transport And Electrical Interface; Revision 1.2
PMBus™ Power System Management Protocol Specification Part II – Command Language;
Revision 1.2
System Management Bus (SMBus) Specification Version 2.0
2.3.5.2
Addressing
The power supply PMBus device address locations are shown below. For redundant systems
there are up to three signals to set the address location of the power supply once it is installed
in the system; Address2, Address1, Address0. For non-redundant systems the power supply
device address location should be B0h.
System addressing
Address2/Address1/
Address0
0/0/0
0/0/1
0/1/0
0/1/1
1/0/0
1/0/1
1/1/0
1/1/1
PMBus device read
addresses 2
B0h/B1h1
B2h/B3h
B4h/B5h
B6h/B7h
B8h/B9h
BAh/BBh
BCh/BDh
BEh/BFh
1
Non-redundant power supplies will use the 0/0/0 address location
2
The addressing method uses the 7 MSB bits to set the address and the LSB to define whether
a device is reading or writing. The addresses defined above use 8 bits including the read/write
bit.
IPMI FRU Addressing