Intel SE7520JR2ATAD2 Product Specification - Page 30

Functional Architecture Intel® Server Board SE7520JR2 High and Low Ratio is determined and programmed to all processors. If there is no value that works for all installed processors, all processors not capable of speeds supported by the BSP are disabled and an error is displayed. 3.1.6.7 Microcode IA-32 processors have the capability of correcting specific errata through the loading of an Intelsupplied data block (i.e., microcode update). The BIOS is responsible for storing the update in non-volatile memory and loading it into each processor during POST. The BIOS allows a number of microcode updates to be stored in the flash, limited by the amount of free space available. The BIOS supports variable size microcode updates. The BIOS verifies the signature prior to storing the update in the flash. 3.1.6.8 Processor Cache The BIOS enables all levels of processor cache as early as possible during POST. There are no user options to modify the cache configuration, size or policies. The largest and highest level cache detected is reported in BIOS Setup. 3.1.6.9 Hyper-Threading Technology Intel® XeonTM processors support Hyper-Threading Technology. The BIOS detects processors that support this feature and enables the feature during POST. BIOS Setup provides an option to selectively enable or disable this feature. The default behavior is "Enabled". The BIOS creates additional entries in the ACPI MP tables to describe the virtual processors. The SMBIOS Type 4 structure shows only the physical processors installed. It does not describe the virtual processors because some operating systems are not able to efficiently utilize the Hyper-Threading Technology. 3.1.6.10 Intel® SpeedStep® Technology Intel® Xeon™ processors support the Geyserville3 (GV3) (whether Geyserville3 is an Intel internal code name?) feature of the Intel® SpeedStep® Technology. This feature changes the processor operating ratio and voltage similar to the Thermal Monitor 2 (TM2) feature. It must be used in conjunction with the TM1 or TM2 feature. The BIOS implements the GV3 feature in conjunction with the TM2 feature. 3.1.6.11 EM64T Technology Support The system BIOS on the Server Board SE7520JR2 supports the Intel Extended Memory 64 technology (EM64T) of the Intel® Xeon™ Processors. There is no BIOS setup option to enable or disable this support. The system will be in IA-32 compatibility mode when booting to an OS. To utilize this feature, a 64-bit capable OS and OS specific drivers are needed. 3.1.7 Multiple Processor Initialization IA-32 processors have a microcode-based bootstrap processor (BSP) arbitration protocol. On reset, all of the processors compete to become the BSP. If a serious error is detected during its Built-in Self-Test (BIST), that processor does not participate in the initialization protocol. A single processor that successfully passes BIST is automatically selected by the hardware as the 30 Revision 1.0 C78844-002