Table of Contents
Intel® Server Board SE7520JR2
Revision 1.0
C78844-002
iv
Table of Contents
1.
Introduction
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19
1.1
Chapter Outline
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19
1.2
Server Board Use Disclaimer
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20
2.
Server Board Overview
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21
2.1
Server Board SE7520JR2 SKU Availability
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21
2.2
Server Board SE7520JR2 Feature Set
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21
3.
Functional Architecture
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26
3.1
Processor Sub-system
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27
3.1.1
Processor Voltage Regulators
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27
3.1.2
Reset Configuration Logic
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27
3.1.3
Processor Module Presence Detection
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27
3.1.4
GTL2006
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27
3.1.5
Common Enabling Kit (CEK) Design Support
........................................................
28
3.1.6
Processor Support
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28
3.1.6.1
Processor Mis-population Detection
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29
3.1.6.2
Mixed Processor Steppings
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29
3.1.6.3
Mixed Processor Models
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29
3.1.6.4
Mixed Processor Families
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29
3.1.6.5
Mixed Processor Cache Sizes
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29
3.1.6.6
Jumperless Processor Speed Settings
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29
3.1.6.7
Microcode
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30
3.1.6.8
Processor Cache
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30
3.1.6.9
Hyper-Threading Technology
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30
3.1.6.10
Intel® SpeedStep® Technology
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30
3.1.6.11
EM64T Technology Support
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30
3.1.7
Multiple Processor Initialization
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30
3.1.8
CPU Thermal Sensors
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31
3.1.9
Processor Thermal Control Sensor
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31
3.1.10
Processor Thermal Trip Shutdown
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31
3.1.11
Processor IERR
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31
3.2
Intel® E7520 Chipset
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31
3.2.1
Memory Controller Hub (MCH)
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32
3.2.1.1
Front Side Bus (FSB)
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32
3.2.1.2
MCH Memory Sub-System Overview
.................................................................
32
3.2.1.3
PCI Express
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32
3.2.1.4
Hub Interface
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33