Intel SE7520JR2ATAD2 Product Specification - Page 52

Functional Architecture Intel® Server Board SE7520JR2 3.4.1.8 Resource Assignment The resource manager assigns the PIC-mode interrupt for the devices that will be accessed by the legacy code. The BIOS configures the PCI Base Address Registers (BAR) and the command register of each device. Software must not make assumptions about the scan order of devices or the order in which resources are allocated to them. The BIOS supports the INT 1Ah PCI BIOS interface calls. 3.4.1.9 Automatic IRQ Assignment The BIOS automatically assigns IRQs to devices in the system for legacy compatibility. No method is provided to manually configure the IRQs for devices. 3.4.1.10 Option ROM Support The BIOS dispatches the option ROMs to available memory space in the address range 0c0000h-0e7fffh. Given the limited space for option ROMs, the BIOS allows for disabling of legacy ROM posting via the BIOS Setup. Onboard and per-slot option ROM disable options are also available in BIOS Setup. The option to disable the onboard video option ROM is not available. The option ROM space is also used by the console redirection binary (if enabled) and the user binary (if present and configured for runtime usage). The SE7520JR2 BIOS integrates option ROMs for the Intel® 82546GB, the ATI* Rage XL, and the LSI* 53C1030 SCSI controller. 3.4.1.11 PCI APIs The system BIOS supports the INT 1Ah, AH = B1h functions as defined in the PCI BIOS Specification. The system BIOS supports the real mode interfaces and does not support the protected mode interfaces. 3.4.2 Split Option ROM The BIOS supports the split option ROM algorithm per the PCI 3.0 specification. 3.4.3 Interrupt Routing The Server Board SE7520JR2 interrupt architecture accommodates both PC-compatible PIC mode and APIC mode interrupts through use of the integrated I/O APICs in the ICH5-R. 3.4.3.1 Legacy Interrupt Routing For PC-compatible mode, the ICH5-R provides two 82C59-compatible interrupt controllers. The two controllers are cascaded with interrupt levels 8-15 entering on level 2 of the primary interrupt controller (standard PC configuration). A single interrupt signal is presented to the processors, to which only one processor will respond for servicing. The ICH5-R contains configuration registers that define which interrupt source logically maps to I/O APIC INTx pins. 52 Revision 1.0 C78844-002