Intel SL3VS Specification Update - Page 24
Intel SL3VS - Celeron 633 MHz Processor Manual
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INTEL® CELERON® PROCESSOR SPECIFICATION UPDATE Summary of Errata NO. CPUID/Stepping Plans 650h 651h 660h 665h 683h 686h 68Ah 6B1h 6B4h A0 A1 A0 B0 B0 C0 D0 A1 B1 ERRATA C53 X X X X X NoFix FLUSH# servicing delayed while waiting for STARTUP_IPI in 2-way MP systems C54 X X X X X NoFix Double ECC error on read may result in BINIT# C55 X X X X X NoFix MCE due to L2 parity error gives L1 MCACOD.LL C56 X X X X X NoFix EFLAGS discrepancy on a page fault after a multiprocessor TLB shootdown C57 X X X X X NoFix Mixed cacheability of lock variables is problematic in MP systems C58 X X X X X NoFix INT 1 with DR7.GD set does not clear DR7.GD C59 X X X X X NoFix Potential loss of data coherency during MP data ownership transfer C60 X X X X X NoFix Misaligned Locked access to APIC space results in a hang C61 X X X X X NoFix Memory ordering based synchronization may cause a livelock condition in MP Systems C62 X X X X X NoFix Processor may assert DRDY# on a write with no data C63 X Fixed Machine check exception may occur due to improper line eviction in the IFU C65 X X NoFix Snoop request may cause DBSY# hang C66 X Fixed MASKMOVQ instruction interaction with string operation may cause deadlock C67 X X X X X NoFix MOVD, CVTSI2SS, or PINSRW Following Zeroing Instruction Can Cause Incorrect Result 16