MSI K9AGM2-FIH User Guide - Page 47

Advanced Chipset Features BIOS Setup DRAM Timing The value in this field depends on performance parameters of the installed memory chips (DRAM). Do not change the value from the factory setting unless you install new memory that has a different performance rating than the original DRAMs. CAS# Latency (Tcl) This controls the CAS latency, which determines the timing delay (in clock cycles) before SDRAM starts a read command after receiving it. M in RAS# Active Time (Tras) This setting determines the time RAS takes to read from and write to a memory cell. RAS# Precharge Time (Trp) This item controls the number of cycles for Row Address Strobe (RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to accumulate its charge before DRAM refresh, refreshing may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the system. RAS# to CAS# Delay (Trcd) W hen DRAM is refreshed, both rows and columns are addressed separately. This setup item allows you to determine the timing of the transition from RAS (row address strobe) to CAS (column address strobe). The less the clock cycles, the faster the DRAM performance. VGA Share Memory Size The system shares memory to the onboard VGA card. This setting controls the exact memory size shared to the VGA card. 3-11