Sharp GX30 Service Manual - Page 127

IC105 VHIYMU762C+-1L YMU762C: SOUND, Pin No., Terminal name, Input/Output, Description of terminal

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IC105 VHIYMU762C+-1L (YMU762C): SOUND Pin No. 1 2 3 4 5* 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Terminal name CLKI LED /IRQ /RST NC PLLC VDD VSS VREF HPOUT-L/MONO HPOUT-R EQ1 EQ2 EQ3 SPVDD SPVSS SPOUT1 SPOUT2 MTR D7 D6 D5 D4 D3 D2 D1 D0 /WR /CS A0 /RD IOVDD Input/Output Input Output Output Input - - - - - Output Output - - - - - Output Output Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input Input - CONFIDENTIAL Description of terminal Clock input terminal External LED control terminal Interrupt output terminal Hardware reset input terminal Not used Built-in PLL capacitor terminal Power supply (Typ + 3.0 V) Ground Analog reference voltage terminal Headphone output L-ch Headphone output R-ch Equalizer terminal 1 Equalizer terminal 2 Equalizer terminal 3 Analog power supply for speaker amplifier (Typ + 3.6 V) Analog ground for speaker amplifier Speaker terminal 1 Speaker terminal 2 External motor control terminal CPU I/F data bus 7 CPU I/F data bus 6 CPU I/F data bus 5 CPU I/F data bus 4 CPU I/F data bus 3 CPU I/F data bus 2 CPU I/F data bus 1 CPU I/F data bus 0 CPU I/F write enable CPU I/F chip select input CPU I/F address signal CPU I/F read enable Power supply for terminal In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside. GX30 Control register SRAM/ROM HPOUT-R HPOUT-L/ MONO IOVDD VDD VSS PLLC CLKI /RST 4 32 7 8 6 1 PLL Timing Generator /CS 29 A0 30 /WR 28 /RD 31 20 ~ 27 D0~D7 CPU interface Interface register Intermediate register FiFO 64 byte FiFO 512 byte Sequencer Buffer /IRQ 3 LED 2 MTR 19 NC 5 LED control Vibrator control TIMER Soft IRQ 11 10 HP Vol R HP Vol L FM + Wave Table Synthesizer R-ch Vol Vol L-ch R-ch 16-bit DAC L-ch Select Mono EQ 12 EQ1 Vol PCM/ADPCM Play back VREF +- SP Vol 13 EQ2 14 EQ3 VREF 9 Analog power supply for speaker amplifier 17 SPOUT1 18 SPOUT2 16 15 VREF SPVSS SPVDD 6 - 7

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GX30
6 – 7
CONFIDENTIAL
IC105 VHIYMU762C+-1L (YMU762C): SOUND
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No.
Terminal name
Input/Output
Description of terminal
1
CLKI
Input
Clock input terminal
2
LED
Output
External LED control terminal
3
/IRQ
Output
Interrupt output terminal
4
/RST
Input
Hardware reset input terminal
5*
NC
–
Not used
6
PLLC
–
Built-in PLL capacitor terminal
7
VDD
–
Power supply (Typ + 3.0 V)
8
VSS
–
Ground
9
VREF
–
Analog reference voltage terminal
10
HPOUT-L/MONO
Output
Headphone output L-ch
11
HPOUT-R
Output
Headphone output R-ch
12
EQ1
–
Equalizer terminal 1
13
EQ2
–
Equalizer terminal 2
14
EQ3
–
Equalizer terminal 3
15
SPVDD
–
Analog power supply for speaker amplifier (Typ + 3.6 V)
16
SPVSS
–
Analog ground for speaker amplifier
17
SPOUT1
Output
Speaker terminal 1
18
SPOUT2
Output
Speaker terminal 2
19
MTR
Output
External motor control terminal
20
D7
Input/Output
CPU I/F data bus 7
21
D6
Input/Output
CPU I/F data bus 6
22
D5
Input/Output
CPU I/F data bus 5
23
D4
Input/Output
CPU I/F data bus 4
24
D3
Input/Output
CPU I/F data bus 3
25
D2
Input/Output
CPU I/F data bus 2
26
D1
Input/Output
CPU I/F data bus 1
27
D0
Input/Output
CPU I/F data bus 0
28
/WR
Input
CPU I/F write enable
29
/CS
Input
CPU I/F chip select input
30
A0
Input
CPU I/F address signal
31
/RD
Input
CPU I/F read enable
32
IOVDD
–
Power supply for terminal
PLL
Timing Generator
FiFO
64 byte
FM +
Wave Table
Synthesizer
PCM/ADPCM
Play back
TIMER
Soft IRQ
LED control
Vibrator control
D0~D7
/RD
/WR
A0
/CS
/RST
/RST
16-bit
DAC
R-ch
L-ch
VREF
EQ
Vol
Select
Mono
HP
Vol R
R-ch
L-ch
HPOUT-R
CLKI
Control register SRAM/ROM
PLLC
VSS
VDD
EQ1
EQ2
EQ3
SPOUT1
SPOUT2
Analog power supply
for speaker amplifier
SPVDD
SPVSS
HPOUT-L/
MONO
11
HP
Vol L
VREF
VREF
1
Vol
Vol
SP
Vol
16 15
9
12
13
14
17
18
10
6
IOVDD
32
8
7
4
29
30
28
31
20 ~ 27
NC
5
/IRQ
3
LED
2
MTR 19
+-
Sequencer
Buffer
FiFO
512 byte
Intermediate register
Interface register
CPU interface