Sharp XL 1700 Service Manual - Page 41

Function Table Of Ic

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XL-1700/1700C FUNCTION TABLE OF IC IC401 VHiLC75342M-1: Function/Volume Equalizer (LC75342M) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12* 13 14 15* 16* 17 18 19* 20 21 22 23 24 25 26 27* 28 29 30 Port Name DI CE VSS TEST LOUT LBASS2 LBASS1 LTRE LIN LSEL0 L4 L3 L2 L1 NC NC R1 R2 R3 R4 RSEL0 RIN RTRE RBASS1 RBASS2 ROUT NC Vref VDD CL Function Serial data and clock input pin for control. Chip enable pin. Data written into an internal latch in a timing of [H] -> [L]. Each analog switch is activated. Data transfer enabled at [H] level. Ground pin. Electronic volume control pin. To be set to the VSS potential. Volume + equalizer output pin. Bass-band filter comprising capacitor and resistor connection pin. Bass-band filter comprising capacitor and resistor connection pin. Capacitor connection pin comprising treble band filter. Volume + equalizer input pin. Input selector output pin. Input signal pin. Input signal pin. Input signal pin. Input signal pin. No CONNECT pin. To be open or connected to VSS. No CONNECT pin. To be open or connected to VSS. Input signal pin. Input signal pin. Input signal pin. Input signal pin. Input selector output pin. Volume + equalizer input pin. Capacitor connection pin comprising treble band filter. Bass-band filter comprising capacitor and resistor connection pin. Bass-band filter comprising capacitor and resistor connection pin. Volume + equalizer output pin. No CONNECT pin. To be open or connected to VSS. 0.5 x VDD voltage generation block for analog ground. Capacitor of several 10µF to be connected between Vref and AWSS (VSS) as a counter measure against power ripple. Supply pin. Serial data and clock input pin for control. In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside. - 41 -

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XL-1700/1700C
FUNCTION TABLE OF IC
IC401
VHiLC75342M-1: Function/Volume Equalizer (LC75342M)
1
DI
Serial data and clock input pin for control.
2
CE
Chip enable pin. Data written into an internal latch in a timing of [H] -> [L]. Each analog switch is activated.
Data transfer enabled at [H] level.
3
VSS
Ground pin.
4
TEST
Electronic volume control pin. To be set to the VSS potential.
5
LOUT
Volume + equalizer output pin.
6
LBASS2
Bass-band filter comprising capacitor and resistor connection pin.
7
LBASS1
Bass-band filter comprising capacitor and resistor connection pin.
8
LTRE
Capacitor connection pin comprising treble band filter.
9
LIN
Volume + equalizer input pin.
10
LSEL0
Input selector output pin.
11
L4
Input signal pin.
12*
L3
Input signal pin.
13
L2
Input signal pin.
14
L1
Input signal pin.
15*
NC
No CONNECT pin. To be open or connected to VSS.
16*
NC
No CONNECT pin. To be open or connected to VSS.
17
R1
Input signal pin.
18
R2
Input signal pin.
19*
R3
Input signal pin.
20
R4
Input signal pin.
21
RSEL0
Input selector output pin.
22
RIN
Volume + equalizer input pin.
23
RTRE
Capacitor connection pin comprising treble band filter.
24
RBASS1
Bass-band filter comprising capacitor and resistor connection pin.
25
RBASS2
Bass-band filter comprising capacitor and resistor connection pin.
26
ROUT
Volume + equalizer output pin.
27*
NC
No CONNECT pin. To be open or connected to VSS.
28
Vref
0.5 x VDD voltage generation block for analog ground. Capacitor of several 10
μ
F to be connected between
Vref and AWSS (VSS) as a counter measure against power ripple.
29
VDD
Supply pin.
30
CL
Serial data and clock input pin for control.
Pin No.
Port Name
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.