ViewSonic VP720B Service Manual - Page 21

Electric Specification

DC Characteristics

Absolute Maximum Ratings

PARAMETER SYMBOL MIN TYP MAX UNITS

Voltage on Input (5V tolerant) VIN -1 5 V

Electrostatic Discharge VESD ±2.5 kV

Latch-Up ILA ±100 mA

Ambient Operating Temperature TA 0 70 oC

Storage temperature (plastic) TSTG -55 125 oC

Thermal Resistance (Junction to Air)

Ө

JA 35.3 oC/W

Table 2 DC Characteristics/Operating Condition

(0'<TA<70'; VDD = 3.3V ± 0.3V)

PARAMETER SYMBOL MIN TYP MAX UNITS

Supply Voltage VDD 3.0 3.3 3.6 V

Output High Voltage VOH 2.4 VDD V

Output Low Voltage VOL GND 0.5 V

Input High Voltage VIH 2.0 V

Input Low Voltage VIL 0.8 V

I/O Pull-up resistance RPU 75K

Ω

I/O Pull-down resistance RPD 75K

Ω

Input Leakage Current(VI=VCC or GND) ILI -10 +10

μ

A

Output Leakage Current(VO=VCC or GND) ILO -20 +20

μ

A

EM6A9320-XXMEtron

4M x 32 DDR SDRAM

Features

±

Fast clock rate: 300/275/250/200 MHz

±

Differential Clock CK & CK# input

±

4 Bi-directional DQS. Data transactions on both edges of DQS (1DQS / Byte)

±

DLL aligns DQ and DQS transitions

±

Edge aligned data & DQS output

±

Center aligned data & DQS input

±

4 internal banks, 1M x 32-bit for each bank

±

Programmable mode and extended mode registers

±

CAS# Latency: 3, 4, 5

±

Burst length: 2, 4, 8

±

Burst Type: Sequential & Interleave

±

Full page burst length for sequential type only

±

Start address of full page burst should be even

±

All inputs except DQ’s & DM are at the positive edge of the system clock

±

No Write-Interrupted by Read function

±

4 individual DM control for write masking only

±

Auto Refresh and Self Refresh

±

4096 refresh cycles / 32ms

±

Power supplies :

VDD = 2.5V _ 5%

VDDQ = 2.5V _ 5%

±

Interface : SSTL_2 I/O compatible

±

Standard 144-ball FBGA package

Overview

The EM6A9320 DDR SDRAM is a high-speed CMOS double data rate synchronous DRAM

containing 128 Mbits. It is internally configured as a quad 1M x 32 DRAM with a synchronous

interface (all signals are registered on the positive edge of the clock signal, CK).Data outputs occur at

both rising edges of CK and CK#.Read and write accesses to the SDRAM are burst oriented; accesses

start at a selected location and continue for a programmed number of locations in a programmed

sequence.Accesses begin with the registration of a BankActivate command, which is then followed by

a Read or Write command.

The EM6A9320 provides programmable Read or Write burst lengths of 2, 4, 8. An auto precharge

function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst

sequence.

ViewSonic Corporation

Confidential – Do Not Copy

VP720-1_VP720b-1

18

ViewSonic VP720B Service Manual - Page 21

Electric Specification, DC Characteristics, PARAMETER SYMBOL MIN TYP MAX UNITS, EM6A9320-XXMEtron,

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