Yamaha E1010 E1010 Owners Manual Image - Page 16

T = 5006 +1 STORED VOLTAGE 0 t 0 0 0 0 0 0 0 0 // 0 IN 1 2 3 4 5 6 7 8 9 10 F OUT 4095 STORAGE REGISTER NUMBER 15 As the samples exit the BBD, they go through a Low Pass Filter which smooths them and restores the original signal. In this illustration, the output appears approximately 100mS after it was input. LOW PASS FILTER NOTE: These samples are very coarse for convenience of illustration; there would normally be many more samples per cycle of audio. Output Signal A Comparison of Analog and Digital Delay Lines A digital delay l ine (DDL) generally incorporates signal conditioning circuitry which is similar to an analog delay l ine (ADL), but has another circuit element, an analog-to-digital (A-D) converter. The A-D converter takes each sample of the waveform and gives it a numerical value to represent its voltage level and polarity (+ or -). These numbers are stored in random access memory (RAM) or in digital shift registers instead of bucket brigade devices. After the desired delay, the numbers are retrieved from memory, go through D-A converters and again become voltage levels. These voltages are rough waveforms and, like the analog delay's BBD output, they must be low pass filtered. The A-D and D-A converters add to the cost of the digital delay line and provide an additional source of noise known as "quantizing noise." The ability of any DDL to handle wide dynamic range and frequency response depends largely on how many digits are used for each number -each stored voltage value. 12-bit (12 digit) DDL's are cheaper, but less desirable than 14-bit, 16-bit or higher resolution DDL's. 12 or more bits may seem like a lot, but remember this is a binary number (base 2), and the polarity, direction of voltage swing, and actual value must all be documented. Similar effects and delay times can be achieved in DDL's and ADL's. The major differences are in cost and performance. The most sophisticated DD L's can yield better audio performance than typical analog delays, but the cost of a DDL is considerably higher than an ADL of comparable audio quality and maximum delay time. Frequency Response versus Delay Time If a longer delay is desired, the clock rate may be slowed down (the E1010 DELAY control is turned up). However, as the clock is slowed down, the duration of each sample time increases, so a larger proportion of High Frequency Superimposed Pure Low Frequency Sine Wave Pure High Frequency Sine Wave on Low Frequency = A A+B LOW PASS FILTER 1:› Output of Bucket Brigade Device when low f equency is applied to input. Note the discrete voltage steps resemble a very high frequency. Output of Delay Line After Post-Delay Conditioning Fig. 12 - High frequencies "Ride" on lower ones and may be filtered out to "Smooth" waveform. the input signal falls into each sample. From Figure 12, it can be seen that high frequencies actually "ride" on low frequencies; they are the smaller "squiggles" superimposed on the dominant waveform. When a larger (coarser) sample is averaged, any small variations within the sample are lost, hence the high frequencies are lost. Thus, slowing the clock rate, while it does lengthen the delay time, also cuts the frequency bandwidth. Another way to increase the delay time maintains the same clock rate but utilizes more storage registers. This is exactly what occurs when the E1010 Delay pushbuttons are switched to a longer delay range. At first it might seem that this technique would provide longer delays with no loss of high frequencies. Due to the way the BBD's function, it is necessary to insert an additional low pass filter with each additional BBD, so there is still some high frequency loss as the delay time increases. However, the signal conditioning (preemphasis and de-emphasis) helps to minimize high frequency roll-off. HOW FAST DOES THE CLOCK RUN? The number of clock pulses per second constitute its rate (frequency). The clock, an oscillator, must be at least twice as fast as the highest audio frequencies one wishes to delay. In real numbers, a 50kHz clock rate would be desirable for a 20kHz upper audio response limit, 30kHz for a 13kHz upper limit, etc. This is why the high frequency response falls off as the clock is slowed down to achieve longer delays. Extremely high clock rates are generally avoided, even though they couldprovide better high frequency response, because (a) more BBD's are required to obtain a given delay, and (b) the relatedhigh-speed circuitry is more complex and costly. How Delay Time Changes Can Produce Pitch Changes Pitch (frequency) is determined by how many waves occur in a given unit of time, i.e. cycles per second. For instance, a 1kHz signal (1,000 cycles/second) is the same as 1 cycle per mill isecond. Normally, any signal applied to the E1010 input is exactly duplicated at its output, but is merely offset in time by a given delay. Thus, one cycle of a 1kHz sine wave would take 1 millisecond to emerge from the output jack of the E1010, but it might come out as much as 300 milliseconds (300mS) after it entered the unit's input. If the delay time is decreased while a signal is coming out of the E1010, then the pitch will be decreased- and vice-versa. For example, if the E1010 delay time is turned down from 300mS to 150mS just as the aforementioned 1kHz wave is emerging, then the wave will