Asus CROSSHAIR IV FORMULA User Guide - Page 168

Debug code table Code 8254TEST 8259MSK1 8259MSK2 8259TEST COUNTMEM MP INIT USB INIT TEST MEM SHOW MP PNP LOGO ONBD IO EN SETUP MSINSTAL CHK ACPI EN CACHE SET CHIP AUTO CFG INIT FDC DET IDE COM/LPT DET FPU CPU CHG EZ FLASH CPR FAIL FAN FAIL UCODEERR FLOPYERR KB ERROR HD ERR CMOS ERR MS ERROR SMARTERR HM ERROR AINETERR CASEOPEN Description Test 8254 Test 8259 interrupt mask bits for channel 1. Test 8259 interrupt mask bits for channel 2. Test 8259 functionality. Calculate total memory by testing the last double word of each 64K page. 1. Program MTRR of M1 CPU 2. Initialize L2 cache for P6 class CPU & program CPU with proper cacheable range. 3. Initialize the APIC for P6 class CPU. 4. On MP platform, adjust the cacheable range to smaller one in case the cacheable ranges between each CPU are not identical. Initialize USB Test all memory (clear all extended memory to 0) Display number of processors (multi-processor platform) Display PnP logo Initialize Onboard IO devices. Okay to enter Setup utility. Initialize PS/2 Mouse Prepare memory size information for function call: INT 15h ax=E820h Turn on L2 cache Program chipset registers according to items described in Setup & Autoconfiguration table. Assign resources to devices. 1. Initialize floppy controller 2. Set up floppy related fields in 40:hardware. Detect & install all IDE devices: HDD, LS120, ZIP, CDROM. Detect serial ports & parallel ports. Detect & install co-processor New CPU installed Execute EZ Flash CPR error Fan error UCODE error Floppy error Keyboard error HDD error CMOS error Mouse error HDD smart function error Hard monitor error AI NET error Case open A-2 Appendix: Debug code table