Asus Terminator Tualatin 786 MANUAL TERMINATOR TUALATIN English V1.0 - Page 89

Chip Configuration

Get Asus Terminator Tualatin PDF manuals and user guides View all Asus Terminator Tualatin manuals
Add to My Manuals
Save this manual to your list of manuals

Page 89 highlights

5.4.1 Chip Configuration SDRAM Timing [By SPD] This sets the optimal timings for items 2-4, depending on the memory modules that you are using. The default setting is [By SPD], which configures items 2-4 by reading the contents in the SPD (Serial Presence Detect) device. The EEPROM on the memory module stores critical parameter information about the module, such as memory type, size, speed, voltage interface, and module banks. Configuration options: [User Defined] [By SPD] SDRAM CAS Latency [3T] This controls the latency between the SDRAM read command and the time that the data actually becomes available. NOTE: This field is configurable only when you set the SDRAM Configuration to [User Defined]. SDRAM RAS to CAS Delay [3T] This controls the latency between the SDRAM active command and the read/write command. NOTE: This field is configurable only when you set the SDRAM Configuration to [User Defined]. SDRAM RAS Precharge Time [3T] This controls the idle clocks after issuing a precharge command to the SDRAM. NOTE: This field is configurable only when you set the SDRAM Configuration to [User Defined]. ASUS Terminator Barebone System 89

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
ASUS Terminator Barebone System
89
5.4.1
Chip Configuration
SDRAM Timing [By SPD]
This sets the optimal timings for items 2–4, depending on the memory
modules that you are using. The default setting is [By SPD], which
configures items 2–4 by reading the contents in the SPD (Serial
Presence Detect) device. The EEPROM on the memory module
stores critical parameter information about the module, such as
memory type, size, speed, voltage interface, and module banks.
Configuration options: [User Defined] [By SPD]
SDRAM CAS Latency [3T]
This controls the latency between the SDRAM read command and
the time that the data actually becomes available.
NOTE:
This field
is configurable only when you set the
SDRAM Configuration
to [User
Defined].
SDRAM RAS to CAS Delay [3T]
This controls the latency between the SDRAM active command and
the read/write command.
NOTE:
This field is configurable only when
you set the
SDRAM Configuration
to [User Defined].
SDRAM RAS Precharge Time [3T]
This controls the idle clocks after issuing a precharge command to
the SDRAM.
NOTE:
This field is configurable only when you set the
SDRAM Configuration
to [User Defined].