Biostar M6VCT M6VCT user's manual - Page 10

Universal Serial Bus, Platform, Dimension, Full Featured Accerated Graphics Port AGP Controller

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Chapter 1 Motherboard Description − Thermal alarm on either external or any combination of two internal temperature sensing circuits. − I/O pad leakage control. Universal Serial Bus − USB v.1.1 and Intel Universal HCI v.1.1 compatible. − Eighteen level (doublewords) data FIFO with full scatter and gather capability. − Root hub and four function ports. − Intrgrated physical layer transceivers with optional over-current detection status on USB inputs. − Keyboard and mouse support. Platform − ATX Form Factor. Dimension − 19.1 cm X 30.6 cm (W x L). Full Featured Accerated Graphics Port (AGP) Controller − Synchronous and pseudo-synchronous with the CPU bus with optimal skew control. − AGP v2.0 compliant. − Supports SideBand Addressing (SBA) mode (non-multiplexed address / data). − Supports 266 MHZ 4x mode for AD and SBA signaling. − Pipelined split-transaction long-burst transfers up to 1GB /sec. − Eight level read request queue. − Four level posted-write request queue. − Thirty-two level (quadworks) read data FIFO (256 bytes). − Sixteen level (quadworks) write data FIFO (128 bytes). − Intelligent request reordering for maximum AGP bus utilization. − Suppots Flush/Fence commands. − Graphics Address Relocation Table (GART). (1)One level TLB structure. (2)Sixteen entry fully associative page table. 1-5

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Chapter 1
Motherboard Description
1-5
−
Thermal alarm on either external or any combination of two internal
temperature sensing circuits.
−
I/O pad leakage control.
Universal Serial Bus
−
USB v.1.1 and Intel Universal HCI v.1.1 compatible.
−
Eighteen level (doublewords) data FIFO with full scatter and gather
capability.
−
Root hub and four function ports.
−
Intrgrated physical layer transceivers with optional over-current
detection status on USB inputs.
−
Keyboard and mouse support.
Platform
−
ATX Form Factor.
Dimension
−
19.1 cm X 30.6 cm (W x L).
Full Featured Accerated Graphics Port (AGP) Controller
−
Synchronous and pseudo-synchronous with the CPU bus with optimal
skew control.
−
AGP v2.0 compliant.
−
Supports SideBand Addressing (SBA) mode (non-multiplexed address
/ data).
−
Supports 266 MHZ 4x mode for AD and SBA signaling.
−
Pipelined split-transaction long-burst transfers up to 1GB /sec.
−
Eight level read request queue.
−
Four level posted-write request queue.
−
Thirty-two level (quadworks) read data FIFO (256 bytes).
−
Sixteen level (quadworks) write data FIFO (128 bytes).
−
Intelligent request reordering for maximum AGP bus utilization.
−
Suppots Flush/Fence commands.
−
Graphics Address Relocation Table (GART).
(1)One level TLB structure.
(2)Sixteen entry fully associative page table.