Compaq ProLiant 1000 Memory technology evolution: an overview of system memory
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- Compaq ProLiant 1000 | Memory technology evolution: an overview of system memory - Page 1
Memory technology evolution: an overview of system memory technologies technology brief, 8th edition Abstract...2 Introduction...2 Basic DRAM operation ...2 DRAM storage density and power consumption 4 Memory access time...4 Chipsets and system bus timing...4 Memory bus speed...5 Burst mode access - Compaq ProLiant 1000 | Memory technology evolution: an overview of system memory - Page 2
Abstract The widening performance gap between processors and memory along with the growth of memoryintensive business applications are driving the need for better memory technologies for servers and workstations. Consequently, there are several memory technologies on the market at any given time. HP - Compaq ProLiant 1000 | Memory technology evolution: an overview of system memory - Page 3
/command bus is a set of traces that carry signals identifying the location of data in memory. The command portion of the address/command bus conveys instructions such as read, write, or refresh. When FPM or EDO memory writes data to a particular cell, the location where the data will be written is - Compaq ProLiant 1000 | Memory technology evolution: an overview of system memory - Page 4
DRAM. For synchronous DRAM, the time is converted to number of memory bus clocks. Chipsets and system bus timing All computer components that execute instructions or transfer data are controlled by a system bus clock. The system chipset controls the speed, or frequency, of the system bus clock and - Compaq ProLiant 1000 | Memory technology evolution: an overview of system memory - Page 5
components, either the rest of the system or the component itself must wait one or more additional clock cycles for data or instructions due to clock resynchronization. In contrast, synchronized components know on which clock cycle data will be available, thus eliminating these timing delays - Compaq ProLiant 1000 | Memory technology evolution: an overview of system memory - Page 6
with every clock cycle after the first access (6-1-1-1) before the memory controller has to send another CAS. Figure 4. Burst mode access. NOP is a "No Operation" instruction. Clock Command Address Data Active NOP NOP Read NOP NOP NOP NOP NOP NOP Row Col Data Data Data Data 64b 64b 64b 64b - Compaq ProLiant 1000 | Memory technology evolution: an overview of system memory - Page 7
Bank interleaving SDRAM divides memory into two to four banks for simultaneous access to more data. This division and simultaneous access is known as interleaving. Using a notebook analogy, two-way interleaving is like dividing each page in a notebook into two parts and having two assistants to each - Compaq ProLiant 1000 | Memory technology evolution: an overview of system memory - Page 8
side. The ninth chip is used to store 4 bits or 8 bits of Error Correction Code, or ECC (see "Parity and ECC DIMMs" sidebar on next page). An ECC DIMM are classified as single-rank or dual-rank. A memory rank is defined as an area or block of 64-bits created by using some or all of the DRAM chips on - Compaq ProLiant 1000 | Memory technology evolution: an overview of system memory - Page 9
on a server has four DIMM slots, the chipset may only be capable of supporting two dual-rank DIMMs or four single rank DIMMs. If two dual-rank DIMMs thus avoiding unreliable operation. To prevent this and other memory-related problems, customers should only use HP-certified DIMMs available in the - Compaq ProLiant 1000 | Memory technology evolution: an overview of system memory - Page 10
Memory channel interleaving Multi-core processors running multi-threaded applications pose a significant challenge to the memory subsystem. The processor cores share the bandwidth of the memory bus; therefore, the multi-core processor's performance is limited by the memory bus bandwidth. Even with - Compaq ProLiant 1000 | Memory technology evolution: an overview of system memory - Page 11
Advanced memory technologies Despite the performance improvement in the overall system due to use of SDRAM, the growing performance gap between the memory and processor must be filled by more advanced memory technologies. These technologies, which are described on the following pages, boost the - Compaq ProLiant 1000 | Memory technology evolution: an overview of system memory - Page 12
Double transition clocking Standard DRAM transfers one data bit to the bus on the rising edge of the bus clock signal, while DDR-1 uses both the rising and falling edges of the clock to trigger the data transfer to the bus (Figure 10). This technique, known as double transition clocking, delivers - Compaq ProLiant 1000 | Memory technology evolution: an overview of system memory - Page 13
DDR-1 DIMMs DDR-1 DIMMs require 184 pins instead of the 168 pins used by standard SDRAM DIMMs. DDR-1 is versatile enough to be used in desktop PCs or servers. To vary the cost of DDR-1 DIMMs for these different markets, memory manufacturers provide unbuffered and registered versions. Unbuffered DDR - Compaq ProLiant 1000 | Memory technology evolution: an overview of system memory - Page 14
signals, and clocks) improves signal integrity by reducing the number of stubs and their length. This feature requires the controller to support "write leveling" on DDR-3 DIMMs. • 1.5-V signaling (compared to 1.8 V for DDR-2) for lower power consumption • A thermal sensor integrated on the DIMM - Compaq ProLiant 1000 | Memory technology evolution: an overview of system memory - Page 15
. The electrical load accumulates as DIMMs are added. These factors decrease the number DIMMs per channel that can be supported as the bus speed increases. For example, Figure 14 shows the number of loads supported per channel at data rates ranging from PC 100 to DDR-3 1600. Note that the number of - Compaq ProLiant 1000 | Memory technology evolution: an overview of system memory - Page 16
Consequently, JEDEC developed the Fully-Buffered DIMM (FB-DIMM) specification, a serial interface that eliminates the parallel stub-bus topology and allows higher memory bandwidth while maintaining or increasing memory capacity. FB-DIMM architecture The FB-DIMM architecture has serial links between - Compaq ProLiant 1000 | Memory technology evolution: an overview of system memory - Page 17
Challenges The challenges for the FB-DIMM architecture include latency and power use (thermal load). Memory latency is the delay from the time the data is requested to the time when the data is available from the memory controller. The FB-DIMM architecture increases this latency in two ways: - Compaq ProLiant 1000 | Memory technology evolution: an overview of system memory - Page 18
rate at 1.2 GHz. This allows for plenty of timing margin in the design of the memory controller. Figure 17. Rambus DRAM RDRAM is capable of supporting up to 32 RDRAM devices on one memory channel while maintaining a 1.2-GHz data rate. Through the use of a repeater chip, even more devices can be - Compaq ProLiant 1000 | Memory technology evolution: an overview of system memory - Page 19
channel is limited to 32 devices, imposing an upper limit on memory capacity supported by a single bus. Use of repeater chips enables use of additional devices DIMMs. HP memory option kits are listed in each server's user guide and in the product QuickSpecs available at www.hp.com. Conclusion The - Compaq ProLiant 1000 | Memory technology evolution: an overview of system memory - Page 20
contained herein is subject to change without notice. The only warranties for HP products and services are set forth in the express warranty statements accompanying such products and services. Nothing herein should be construed as constituting an additional warranty. HP shall not be liable
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Memory technology evolution: an overview
of system memory technologies
technology brief, 8
th
edition
Abstract
..............................................................................................................................................
2
Introduction
.........................................................................................................................................
2
Basic DRAM operation
.........................................................................................................................
2
DRAM storage density and power consumption
...................................................................................
4
Memory access time
.........................................................................................................................
4
Chipsets and system bus timing
..........................................................................................................
4
Memory bus speed
...........................................................................................................................
5
Burst mode access
............................................................................................................................
5
SDRAM technology
..............................................................................................................................
6
Bank interleaving
.............................................................................................................................
7
Increased bandwidth
........................................................................................................................
7
Registered SDRAM modules
..............................................................................................................
7
DIMM Configurations
.......................................................................................................................
8
Single-sided and double-sided DIMMs
............................................................................................
8
Single-rank, dual-rank, and quad-rank DIMMs
.................................................................................
8
Rank interleaving
..........................................................................................................................
9
Memory channel interleaving
..........................................................................................................
10
Advanced memory technologies
..........................................................................................................
11
Double Data Rate SDRAM technologies
............................................................................................
11
DDR-1
.......................................................................................................................................
11
DDR-2
.......................................................................................................................................
13
DDR-3
.......................................................................................................................................
14
Module naming convention and peak bandwidth
...........................................................................
14
Fully-Buffered DIMMs
......................................................................................................................
15
FB-DIMM architecture
..................................................................................................................
16
Challenges
................................................................................................................................
17
Rambus DRAM
..............................................................................................................................
18
Importance of using HP-certified memory modules in ProLiant servers
.......................................................
19
Conclusion
........................................................................................................................................
19
For more information
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20
Call to action
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20