Intel BX80539T2500 User Manual - Page 28
Intel BX80539T2500 - Core Duo 2 GHz Processor Manual
UPC - 735858180054
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3.3.5 3.3.6 3.3.7 Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with IntelD®eEv7e5lo2p0mCehnipt sKeitt • PCI 2.2 Interface • Two serial I/O ports • Two-stage WDT (Watch Dog Timer) • LPC Interface • EPLD for Port 80 decode and display • FWH Interface • SMBus 2.0 controller • I/O APIC • Four USB 2.0 Ports Intel® 6700PXH PCI Hub TacboihtPneCPfi6ICge7Iu0crde0hedPavXnitcHnoeesPpl..CroTI-vhXied1e63s73a00McPoHXnzHnaePncCtdiIotnHheubbeottcwhoeenretnatointhPseCtIwE-7oX5P12C00I0abMnudHsPzi,nCtfIeoorrfraePcitCehsIe-rXth3ian2tt-ehbraiftvaoecrebs6e4ve-ina • Two PCI-X 100 MHz slots • One PCI-X 133 MHz slot Intel® 82571EB Gigabit Ethernet Controller 8TMtTfpurXh2oaAler5l,fCytf7asiIci1na.nnEntdaUteeBdcs1lgreP8o0prsHas2rBostt5AYehv7iSdeitE1dsEteEGPh-tTsCBiregaIraaGannEpbissegxptiattaaplcilbcnErateaiidtyothstaenisEeorr,trdnXhnflsiu4IeenEnr(tkcnE8c,oMteE0inateo2nn8dnC.ed03isoac2,,pnt.8Atiht3ohr0cynoeEc2sletli.tcech3sooaresuntlri,/hCstnlraoeoeoangntlIdlistneciirnantr8oetlg0lmell®l2(raeafM.y,a3nEeAccaa7reoCgb5sm).)fe2o.spa0rInaPnM1cdC0tCaIp0cdHhEo0d.yxmBitsTpAiiphorcSoeenaEsnlIts-elnoTan,ptymtea1elwc0ark0in(teBahPtgAHtiSwYnE)go- Memory Subsystem The memory subsystem is designed to support Double Data Rate 2 (DDR2) Synchronous Dynamic Random Access Memory (SDRAM) using the Intel® E7520 MCH. TThhee pMeCaHk pbraonvdidweidstthwoof ienadcehpeDnDdRe2ntbDraDnRchchchaannnnelesl,isw3hi.c2hGsBuyptpeo/rst(D8DbRy2te-4s0x04D0I0MMMTs/.s) with DDR2-400. When the two DDR2 channels from the MCH operate in lock step, the eDfDfeRc2ti-v4e00ov. erall peak bandwidth of the DDR2 memory subsystem is 6.4 GByte/s for Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset Development Kit User's Manual January 2007 28 Order Number: 316068-001US